IR3871MPBF 查看數據表（PDF） - International Rectifier

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IR3871MPBF

8A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR

International Rectifier 

CIRCUIT DESCRIPTION

UNDER/OVER VOLTAGE MONITOR

The IR3871 monitors the voltage at the FB node

through a 350ns filter. If the FB voltage is below

the under voltage threshold, UV# is set to LOW

holding PGOOD to be LOW. If the FB voltage is

above the over voltage threshold, OV# is set to

LOW, the shutdown signal (SD) is set to HIGH,

MOSFET gates are turned off, and PGOOD

signal is pulled low. Toggling VCC or EN will

allow the next start up. Figure 19 shows

PGOOD status change when UV/OV is

detected. The over voltage and under voltage

thresholds can be found in the Electrical

Specification section.

IR3871MPBF

OVER CURRENT MONITOR

The over-current circuitry monitors the output

current during each switching cycle. The voltage

across the lower MOSFET, VPHASE, is

monitored for over current and zero crossing. The

OCP circuit evaluates VPHASE for an over

current condition typically 270ns after the lower

MOSFET is gated on. This delay functions to filter

out switching noise. The minimum lower gate

interval allows time to sample VPHASE.

The over current trip point is programmed with a

resistor from the ISET pin to PHASE pin, as

shown in equation 4, where Tj is the junction

temperature of Q2 at operation conditions, and 0.4

is the temperature coefficient (~4000 ppm/C) of

Q2 RDSON. When over current is detected, the

output gates are tri-state and SS voltage is pulled

to 0V. This initiates a new soft start cycle. If there

is a total of four OC events, the IR3871 will

disable switching, as shown in Figure 20. Toggling

VCC or EN will allow the next start up.

RSET  RDSON  IOC  (1 Tj  25  0.4) (4)

20 A

100

Figure 19(a). Under/Over Voltage Monitor

* typical filter delay

Figure 19(b). Over Voltage Protection

Figure 20. Over Current Protection

12

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