IR3871MPBF 查看數據表（PDF） - International Rectifier

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IR3871MPBF

8A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR

International Rectifier 

CIRCUIT DESCRIPTION

GATE DRIVE LOGIC

The gate drive logic features adaptive dead

time, diode emulation, and a minimum lower

gate interval.

An adaptive dead time prevents the

simultaneous conduction of the upper and lower

MOSFETs. The lower gate voltage (LGATE)

must be below approximately 1V after PWM

goes HIGH before the upper MOSFET can be

gated on. Also, the upper gate voltage

(UGATE), the difference voltage between

UGATE and PHASE, must be below

approximately 1V after PWM goes LOW before

the lower MOSFET can be gated on.

The control MOSFET is gated on after the

adaptive delay for PWM = HIGH and the

synchronous MOSFET is gated on after the

adaptive delay for PWM = LOW. The lower

MOSFET is driven ‘off’ when the signal

ZCROSS indicates that the inductor current has

reversed as detected by the PHASE voltage

crossing the zero current threshold. The

synchronous MOSFET stays ‘off’ until the next

PWM falling edge. When the lower peak of

inductor current is above zero, a forced

continuous current condition is selected. The

control MOSFET is gated on after the adaptive

delay for PWM = HIGH, and the synchronous

MOSFET is gated on after the adaptive delay for

PWM = LOW.

The synchronous MOSFET gate is driven on for

a minimum duration. This minimum duration

allows time to recharge the bootstrap capacitor

and allows the current monitor to sample the

PHASE voltage.

IR3871MPBF

STABILITY CONSIDERATIONS

Constant-on-time control is a fast , ripple based

control scheme. Unstable operation can occur

if certain conditions are not met. The system

instability is usually caused by:

• Switching noise coupled to FB input. This

causes the PWM comparator to trigger

prematurely after the 400ns minimum Q2 on-

time. It will result in double or multiple pulses

every switching cycle instead of the expected

single pulse. Double pulsing can causes

higher output voltage ripple, but in most

application it will not affect operation. This can

usually be prevented by careful layout of the

ground plane and the FB sensing trace.

• Steady state ripple on FB pin being too small.

The PWM comparator in IR3871 requires

minimum 7mVp-p ripple voltage to operate

stably. Not enough ripple will result in similar

double pulsing issue described above. Solving

this may require using output capacitors with

higher ESR.

• ESR loop instability. The stability criteria of

constant on-time is: ESR*Cout>Ton/2. If ESR

is too small that this criteria is violated then

sub-harmonic oscillation will occur. This is

similar to the instability problem of peak-

current-mode control with D>0.5. Increasing

ESR is the most effective way to stabilize the

system, but the price paid is the larger output

voltage ripple.

• For applications with all ceramic output

capacitors, the ESR is usually too small to

meet the stability criteria. In these

applications, external slope compensation is

necessary to make the loop stable. The ramp

injection circuit, composed of R6, C13, and

C14, shown in Figure 7 is required. The

inductor current ripple sensed by R6 and C13

is AC coupled to the FB pin through C14. C14

is usually chosen between 1 to 10nF, and C13

between 10 to 100nF. R6 should then be

chosen such that L/DCR = C13*R6.

13

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