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IR3871MPBF

8A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR

International Rectifier 

IR3871MPBF

COMPONENT SELECTION

Selection of components for the converter is an

iterative process which involves meeting the

specifications and trade-offs between

performance and cost. The following sections will

guide one through the process.

INDUCTOR SELECTION

Inductor selection involves meeting the steady

state output ripple requirement, minimizing the

switching loss of upper MOSFETs, meeting

transient response specifications and minimizing

the output capacitance. The output voltage

includes a DC voltage and a small AC ripple

component due to the low pass filter which has

incomplete attenuation of the switching

harmonics. Neglecting the inductance in series

with the output capacitor, the magnitude of the AC

voltage ripple is determined by the total inductor

ripple current flowing through the total equivalent

series resistance (ESR) of the output capacitor

bank.

  ΔI  TON  VIN  VOUT (5)

2L

One can use equation 5 to find the required

inductance. ΔI is defined as shown in Figure 21.

The main advantage of small inductance is

increased inductor current slew rate during a load

transient, which leads to a smaller output

capacitance requirement as discussed in the

Output Capacitor Selection section. The draw

back of using smaller inductances is increased

switching power loss in upper MOSFET, which

reduces the system efficiency and increases the

thermal dissipation.

INPUT CAPACITOR SELECTION

The main function of the input capacitor bank is

to provide the input ripple current and fast slew

rate current during the load current step up. The

input capacitor bank must have adequate ripple

current carrying capability to handle the total

RMS current. Figure 21 shows a typical input

current. Equation 6 shows the RMS input

current. The RMS input current contains the DC

load current and the inductor ripple current. As

shown in equation 5, the inductor ripple current

is unrelated to the load current. The maximum

RMS input current occurs at the maximum

output current. The maximum power dissipation

in the input capacitor equals the square of the

maximum RMS input current times the input

capacitor’s total ESR.

IOUT

Input Current

ΔI

TS

Figure 21. Typical Input Current Waveform.

   IIN_RMS 

1

Ts

 f2

t

 dt

Ts 0

 IOUT 

Ton  Fs 

1 1 

ΔI

2





(6)

3  IOUT 

The voltage rating of the input capacitor needs

to be greater than the maximum input voltage

because of high frequency ringing at the phase

node. The typical percentage is 25%.

14

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