IR3871MPBF 查看數據表（PDF） - International Rectifier

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IR3871MPBF

8A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR

International Rectifier 

IR3871MPBF

COMPONENT SELECTION

OUTPUT CAPACITOR SELECTION

Selection of the output capacitor requires meeting

voltage overshoot requirements during load

removal, and meeting steady state output ripple

voltage requirements. The output capacitor is the

most expensive converter component and

increases the overall system cost. The output

capacitor decoupling in the converter typically

includes the low frequency capacitor, such as

Specialty Polymer Aluminum, and mid frequency

ceramic capacitors.

The second purpose of the output capacitor is to

minimize the overshoot of the output voltage

when the load decreases as shown in Figure

23. By using the law of energy before and after

the load removal, equation 8 shows the output

capacitance requirement for a load step.

COUT



L  ISTEP 2

VOS2  VOUT 2

(8)

The first purpose of output capacitors is to provide

current when the load demand exceeds the

inductor current, as shown in Figure 22. Equation

7 shows the charge requirement for a certain load.

The advantage provided by the IR3871 at a load

step is to reduce the delay compared to a fixed

frequency control method (in microseconds or (1-

D)*Ts). If the load increases right after the PWM

signal goes low, the longest delay will be equal to

the minimum lower gate on as shown in the

Electrical Specification table. The IR3871 also

reduces the inductor current slew time, the time it

takes for the inductor current to reach equality

with the output current, by increasing the

switching frequency up to 2.5MHz. The result

reduces the recovery time.

Load

Current

Output

Charge

ISTEP

Inductor

Slew

Rate

VOUT

VL

VDROP VESR

VOS

IOUT

ISTEP

Figure 23. Typical Output Voltage Response

Waveform.

BOOT CAPACITOR SELECTION

The boot capacitor starts the cycle fully charged

to a voltage of VB(0). Cg equals 0.65nF in

IR3871. Choose a sufficiently small ΔV such

that VB(0)-ΔV exceeds the maximum gate

threshold voltage to turn on the high side

MOSFET.

CBOOT



Cg

 



VB (0)

ΔV

1



(9)

Δt

t

Figure 22. Charge Requirement during Load Step

Q  C  V  0.5 Istep t (7a)

  COUT



1

VDROP

1

 2



L  Istep2

VIN  VOUT





(7b)

The output voltage drop, VDROP, initially depends

on the characteristic of the output capacitor.

VDROP is the sum of the equivalent series

inductance (ESL) of the output capacitor times the

rate of change of the output current and the ESR

times the change of the output current. VESR is

usually much greater than VESL. The IR3871

requires a total ESR such that the ripple voltage at

the FB pin is greater than 7mV.

Choose a boot capacitor value larger than the

calculated CBOOT in equation 9. Equation 9 is

based on charge balance at CCM operation.

Usually the boot capacitor will be discharged to

a much lower voltage when the circuit is

operating in DCM mode at light load, due to

much longer Q2 off time and the bias current

drawn by the IC. Boot capacitance needs to be

increased if insufficient turn-on of Q1 is

observed at light load, typically larger than

0.1µF is needed. The voltage rating of this part

needs to be larger than VB(0) plus the desired

derating voltage. Its ESR and ESL needs to be

low in order to allow it to deliver the large

current and di/dt’s which drive MOSFETs most

efficiently. In support of these requirements a

ceramic capacitor should be chosen.

15

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