AM29F004BB-90 查看數據表（PDF） - Spansion Inc.
零件编号
产品描述 (功能)
生产厂家
AM29F004BB-90 Datasheet PDF : 37 Pages
| |||
DATA SHEET
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or
whether the device entered the Erase Suspend mode. Toggle
Bit I may be read at any address, and is valid after the rising
edge of the final WE# pulse in the command sequence (prior
to the program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause DQ6 to toggle.
(The system may use either OE# or CE# to control the read
cycles.) When the operation is complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for approxi-
mately 100 μs, then returns to reading array data. If not all
selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the
device enters the Erase Suspend mode, DQ6 stops toggling.
However, the system must also use DQ2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see the subsection on DQ7: Data#
Polling).
If a program address falls within a protected sector, DQ6
toggles for approximately 2 µs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 6 for the toggle bit algo-
rithm, and to the Toggle Bit Timings figure in the “AC
Characteristics” section for the timing diagram. The DQ2 vs.
DQ6 figure shows the differences between DQ2 and DQ6 in
graphical form. See also the subsection on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within
those sectors that were selected for erasure. (The system
may use either OE# or CE# to control the read cycles.) But
DQ2 cannot distinguish whether the sector is actively erasing
or is erase-suspended. DQ6, by comparison, indicates
whether the device is actively erasing, or is in Erase Sus-
pend, but cannot distinguish which sectors are selected for
erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 6 on page 19 to compare
outputs for DQ2 and DQ6.
Figure 6, on page 19 shows the toggle bit algorithm in flow-
chart form, and the section DQ2: Toggle Bit II on page 18
explains the algorithm. See also the DQ6: Toggle Bit I on
page 18 subsection. Refer to the Toggle Bit Timings figure for
the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows
the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 19 for the following discussion.
Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to deter-
mine whether a toggle bit is toggling. Typically, a system
would note and store the value of the toggle bit after the first
read. After the second read, the system would compare the
new value of the toggle bit with the first. If the toggle bit is not
toggling, the device completed the program or erase opera-
tion. The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system deter-
mines that the toggle bit is still toggling, the system also
should note whether the value of DQ5 is high (see the section
on DQ5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as DQ5 went high. If the toggle bit
is no longer toggling, the device successfully completed the
program or erase operation. If it is still toggling, the device did
not complete the operation successfully, and the system must
write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and DQ5 has not gone high. The
system may continue to monitor the toggle bit and DQ5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figure
6, on page 19).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time exceeded
a specified internal pulse count limit. Under these conditions
DQ5 produces a 1. This is a failure condition that indicates
the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to
program a 1 to a location that is previously programmed to 0.
Only an erase operation can change a “0” back to a 1.
Under this condition, the device halts the operation, and
when the operation exceeds the timing limits, DQ5 produces
a 1.
Under both these conditions, the system must issue the reset
command to return the device to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read DQ3 to determine whether or not an erase opera-
tion started. (The sector erase timer does not apply to the
chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional
sector erase command. When the time-out is complete, DQ3
switches from 0 to 1. The system may ignore DQ3 if the
system can guarantee that the time between additional sector
18
Am29F004B
Am29F004B_00_E4 May 9, 2006
Share Link: 