EVAL-ADN2811-CML 查看數據表（PDF） - Analog Devices
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EVAL-ADN2811-CML Datasheet PDF : 20 Pages
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ADN2811
FUNCTIONAL DESCRIPTION
CLOCK AND DATA RECOVERY
The ADN2811 recovers clock and data from serial bit streams at
OC-48 as well as the 15/14 FEC rates. The data rate is selected
by the RATE input (see Table 4).
Table 4. Data Rate Selection
RATE
Data Rate
0
OC-48
1
OC-48 FEC
Frequency (MHz)
2488.32
2666.06
LIMITING AMPLIFIER
The limiting amplifier has differential inputs (PIN/NIN) that
are internally terminated with 50 Ω to an on-chip voltage ref-
erence (VREF = 0.6 V typically). These inputs are normally
ac-coupled, although dc coupling is possible as long as the input
common-mode voltage remains above 0.4 V (see Figure 22,
Figure 23, and Figure 24). Input offset is factory trimmed to
achieve better than 4 mV typical sensitivity with minimal drift.
The limiting amplifier can be driven differentially or single-
ended.
SLICE ADJUST
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise by
applying a differential voltage input of ±0.8 V to SLICEP/N
inputs. If no adjustment of the slice level is needed, SLICEP/N
must be tied to VCC.
LOSS OF SIGNAL (LOS) DETECTOR
The receiver front end level signal detect circuit indicates when
the input signal level has fallen below a user adjustable threshold.
The threshold is set with a single external resistor from Pin 1,
THRADJ, to GND. The LOS comparator trip point versus the
resistor value is illustrated in Figure 4 (this is only valid for
SLICEP = SLICEN = VCC). If the input level to the ADN2811
drops below the programmed LOS threshold, SDOUT (Pin 45)
indicates the loss of signal condition with a Logic 1. The LOS
response time is ~300 ns by design, but is dominated by the RC
time constant in ac-coupled applications.
If using the LOS detector, the quantizer slice adjust pins must
both be tied to VCC. This is to avoid interaction with the LOS
threshold level.
Note that it is not expected to use both LOS and slice adjust at
the same time; systems with optical amplifiers need the slice
adjust to evade ASE. However, a loss of signal in an optical link
that uses optical amplifiers causes the optical amplifier output
to be full-scale noise. Under this condition, the LOS does not
detect the failure. In this case, the loss of lock signal indicates
the failure because the CDR circuitry is unable to lock onto a
signal that is full-scale noise.
Data Sheet
REFERENCE CLOCK
There are three options for providing the reference frequency to
the ADN2811: differential clock, single-ended clock, or crystal
oscillator. See Figure 14, Figure 15, and Figure 16 for example
configurations.
ADN2811
REFCLKP
BUFFER
REFCLKN
VCC
VCC
XO1
XO2
100kΩ 100kΩ
VCC/2
CRYSTAL
OSCILLATOR
VCC
REFSEL
Figure 14. Differential REFCLK Configuration
VCC
CLK
OSC OUT
REFCLKP
REFCLKN
NC
ADN2811
BUFFER
VCC
VCC
XO1
XO2
100kΩ 100kΩ
VCC/2
CRYSTAL
OSCILLATOR
VCC
REFSEL
Figure 15. Single-Ended REFCLK Configuration
ADN2811
VCC
REFCLKP
NC
REFCLKN
19.44MHz
XO1
XO2
BUFFER
100kΩ 100kΩ
VCC/2
CRYSTAL
OSCILLATOR
REFSEL
Figure 16. Crystal Oscillator Configuration
Rev. C | Page 12 of 20
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