ADN2817ACP-RL7 查看數據表（PDF） - Analog Devices

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ADN2817ACP-RL7

Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs

Analog Devices 

ADN2817/ADN2818

Preliminary Technical Data

Table 14. BERCTLA

Set BER Timer

D7 D6 D5

0 0 0 = 218 bits

0 0 1 = 221 bits

0 1 0 = 224 bits

0 1 1 = 227 bits

1 0 0 = 230 bits

1 0 1 = 233 bits

1 1 0 = 236 bits

1 1 1 = 239 bits

Phase Polarity

D4

0= Positive

1= Negative

BER Start Pulse

D3

Write a “1” followed by “0” to

initiate BER measurement

Error Count Byte Select

D2 D1 D0

0 0 0 = Byte 0

0 0 1 = Byte 1

0 1 0 = Byte 2

0 1 1 = Byte 3

1 0 0 = Byte 4

1 0 1 = Byte 5

Table 15. BERCTLB

Enable BER

D7

D6

D5

Set to 0 Set to 0 0= BER Disabled

1= BER Enabled

BER Standby Mode

D4

0= BER meas enabled

1= BER meas in Stdby mode

Clock XOR Input

D3

Write a “1” followed by “0” to clock

input to XOR

BER Mode

D2 D1 D0

0 0 0 = NDC -> OB

0 0 1 = DDC -> OB

0 1 0 = DIV0 -> OB

0 1 1 = DIV1 -> OB

1 0 0 = CLK0,1 -> OB

1 0 1 = NDC -> PRBS

1 1 0 = DDC -> PRBS

Rev. PrA | Page 14 of 35

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