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ADN2817ACP

Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs

Analog Devices 

Preliminary Technical Data

Continuous Rate 12.3Mb/s to 2.7Gb/s

Clock and Data Recovery ICs

ADN2817/ADN2818

FEATURES

Serial data input: 12.3 Mb/s to 2.7 Gb/s

Exceeds ITU-T Jitter Specifications

Integrated Limiting Amp: 6mV sensitivity (ADN2817 only)

Adjustable slice level: ±100 mV (ADN2817 only)

Patented dual-loop clock recovery architecture

Programmable LOS detect (ADN2817 only)

Slice level and sample phase adjustments (ADN2817 only)

Integrated PRBS Generator and Detector

No reference clock required

Loss of lock indicator

Supports Double Data Rate

Relative Bit Error Rate Monitor

Rate Selectivity without the use of a reference clock

I2C™ interface to access optional features

Single-supply operation: 3.3 V

Low power: 650/600 mW (ADN2817/ADN2818)

5 mm × 5 mm 32-lead LFCSP

APPLICATIONS

SONET OC-1/3/12/48 and all associated FEC rates

Fibre Channel, 2× Fibre Channel , GbE, HDTV, etc.

WDM transponders

Regenerators/repeaters

Test equipment

FUNCTIONAL

BLOCK DIAGRAM

REFCLKP/N

(optional)

LOL

PRODUCT DESCRIPTION

The ADN2817/ADN2818 provides the receiver functions of

quantization, signal level detect, and clock and data recovery for

continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The

ADN2817/ADN2818 automatically locks to all data rates

without the need for an external reference clock or

programming. All SONET jitter requirements are exceeded,

including jitter transfer, jitter generation, and jitter tolerance.

All specifications are quoted for −40°C to +85°C ambient

temperature, unless otherwise noted.

This device, together with a PIN diode and a TIA preamplifier,

can implement a highly integrated, low cost, low power fiber

optic receiver.

The ADN2817/ADN2818 have many optional features available

via an I2C interface, e.g. the user can read back the data rate that

the ADN2817/ADN2818 is locked on to, or the user can set the

device to only lock to one particular data rate if provisioning of

data rates is required.

The ADN2817/ADN2818 is available in a compact 5 mm × 5

mm 32-lead chip scale package.

CF1

CF2

VCC VEE

SLICEP/N

Slice Adjust

(ADN2817

only)

PIN

NIN

Phase

Shifter

VREF

LOS Detect

(ADN2817

only)

Data

Re-Timing

Freq/

Lock

Det

Phase

Det.

Loop

Filter

Loop

Filter

THRADJ SDOUT DATAOUTP/N

CLKOUTP/N

Σ

VCO

I2C

Registers

SCK SDA

Figure 1 ADN2817/ADN2818 Functional Block Diagram

Rev.PrA

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However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703 © 2006 Analog Devices, Inc. All rights reserved.

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