ADXL343 查看數據表（PDF） - Analog Devices
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ADXL343 Datasheet PDF : 36 Pages
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Data Sheet
Table 9. SPI Digital Input/Output
Parameter
Digital Input
Low Level Input Voltage (VIL)
High Level Input Voltage (VIH)
Low Level Input Current (IIL)
High Level Input Current (IIH)
Digital Output
Low Level Output Voltage (VOL)
High Level Output Voltage (VOH)
Low Level Output Current (IOL)
High Level Output Current (IOH)
Pin Capacitance
Test Conditions
VIN = VDD I/O
VIN = 0 V
IOL = 10 mA
IOH = −4 mA
VOL = VOL, max
VOH = VOH, min
fIN = 1 MHz, VIN = 2.5 V
1 Limits based on characterization results, not production tested.
ADXL343
Limit1
Min
Max
0.7 × VDD I/O
−0.1
0.3 × VDD I/O
0.1
0.8 × VDD I/O
10
0.2 × VDD I/O
−4
8
Unit
V
V
µA
µA
V
V
mA
mA
pF
Table 10. SPI Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)1
Limit2, 3
Parameter Min
Max Unit Description
fSCLK
5
MHz SPI clock frequency
tSCLK
200
ns
1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40
tDELAY
5
ns
CS falling edge to SCLK falling edge
tQUIET
5
ns
SCLK rising edge to CS rising edge
tDIS
10
ns
CS rising edge to SDO disabled
tCS,DIS
150
ns
CS deassertion between SPI communications
tS
0.3 × tSCLK
ns
SCLK low pulse width (space)
tM
0.3 × tSCLK
ns
SCLK high pulse width (mark)
tSETUP
5
ns
SDI valid before SCLK rising edge
tHOLD
5
ns
SDI valid after SCLK rising edge
tSDO
40
ns
SCLK falling edge to SDO/SDIO output transition
tR 4
20
ns
SDO/SDIO output high to output low transition
tF4
20
ns
SDO/SDIO output low to output high transition
1 The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation.
2 Limits based on characterization results, characterized with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested.
3 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9.
4 Output rise and fall times measured with capacitive load of 150 pF.
Rev. 0 | Page 15 of 36
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