ADSP-21367BBP-2A 查看數據表（PDF） - Analog Devices

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ADSP-21367BBP-2A

SHARC Processors

Analog Devices 

ADSP-21367/ADSP-21368/ADSP-21369

Reset

Table 15. Reset

Parameter

Min

Max

Unit

Timing Requirements

t1

WRST

RESET Pulse Width Low

4tCK

ns

tSRST

RESET Setup Before CLKIN Low

8

ns

1 Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming stable

VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

RESET

tWRST

tSRST

Figure 8. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 16. Interrupts

Parameter

Timing Requirement

tIPW

IRQx Pulse Width

Min

2 × tPCLK + 2

DAI_P20-1

DPI_14-1

FLAG2-0

(IRQ2-0)

tIPW

Figure 9. Interrupts

Max

Unit

ns

Rev. C | Page 21 of 56 | January 2008

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