A3983SLPTR-T(2009) 查看數據表（PDF） - Allegro MicroSystems

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A3983SLPTR-T
(Rev.:2009)

DMOS Microstepping Driver with Translator

Allegro MicroSystems 

A3983

DMOS Microstepping Driver with Translator

Package LP

CP1 1

CP2 2

VCP 3

VREG 4

MS1 5

MS2 6

RESET 7

ROSC 8

SLEEP 9

VDD 10

STEP 11

REF 12

PAD

24 GND

23 ENABLE

22 OUT2B

21 VBB2

20 SENSE2

19 OUT2A

18 OUT1A

17 SENSE1

16 VBB1

15 OUT1B

14 DIR

13 GND

Terminal List Table

Name

Number

Package LP

Description

CP1

1

Charge pump capacitor terminal

CP2

2

Charge pump capacitor terminal

VCP

3

Reservoir capacitor terminal

VREG

4

Regulator decoupling terminal

MS1

5

Logic input

MS2

6

Logic input

RESET

7

Logic input

ROSC

8

Timing set

SLEEP

9

Logic input

VDD

10

Logic supply

STEP

11

Logic input

REF

GND

12

13, 24

Gm reference voltage input

Ground*

DIR

14

Logic input

OUT1B

15

DMOS Full Bridge 1 Output B

VBB1

16

Load supply

SENSE1

17

Sense resistor terminal for Bridge 1

OUT1A

18

DMOS Full Bridge 1 Output A

OUT2A

19

DMOS Full Bridge 2 Output A

SENSE2

20

Sense resistor terminal for Bridge 2

VBB2

21

Load supply

OUT2B

22

DMOS Full Bridge 2 Output B

ENABLE

23

Logic input

NC

–

No connection

PAD

–

Exposed pad for enhanced thermal dissipation*

*The GND pins must be tied together externally by connecting to the PAD ground plane

under the device.

Allegro MicroSystems, Inc.

11

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

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