DSP56F826 查看數據表（PDF） - Motorola => Freescale

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DSP56F826

16-bit Hybrid Controller

Motorola => Freescale 

Freescale Semiconductor, Inc.

Table 3. 56F826 Signal and Package Information for the 100 Pin LQFP

Signal

Name

Pin No.

Type

Description

TXD1

93

Output

Transmit Data (TXD1)—transmit data output

(MISO0)

Input/Output

SPI Master In/Slave Out—This serial data pin is an input to a master

device and an output from a slave device. The MISO line of a slave

device is placed in the high-impedance state if the slave device is not

selected.

After reset, the default state is SCI output.

RXD1

92

Input

Receive Data (RXD1)— receive data input

(Schmitt)

(SS0)

Input

SPI Slave Select—In master mode, this pin is used to arbitrate multiple

masters. In slave mode, this pin is used to select the slave.

After reset, the default state is SCI input.

IRQA

32

Input

External Interrupt Request A—The IRQA input is a synchronized

(Schmitt) external interrupt request that indicates that an external device is

requesting service. It can be programmed to be level-sensitive or

negative-edge-triggered. If level-sensitive triggering is selected, an

external pull-up resistor is required for wired-OR operation.

If the processor is in the Stop state and IRQA is asserted, the processor

will exit the Stop state.

IRQB

33

Input

External Interrupt Request B—The IRQB input is an external interrupt

(Schmitt) request that indicates that an external device is requesting service. It can

be programmed to be level-sensitive or negative-edge-triggered. If level-

sensitive triggering is selected, an external pull-up resistor is required for

wired-OR operation.

RESET

45

Input

Reset—This input is a direct hardware reset on the processor. When

(Schmitt) RESET is asserted low, the device is initialized and placed in the Reset

state. A Schmitt trigger input is used for noise immunity. When the

RESET pin is deasserted, the initial chip operating mode is latched from

the external boot pin. The internal reset signal will be deasserted

synchronous with the internal clocks, after a fixed number of internal

clocks.

To ensure complete hardware reset, RESET and TRST should be

asserted together. The only exception occurs in a debugging

environment when a hardware device reset is required and it is

necessary not to reset the OnCE/JTAG module. In this case, assert

RESET, but do not assert TRST.

EXTBOOT

25

Input

(Schmitt)

External Boot—This input is tied to VDD to force device to boot from off-

chip memory. Otherwise, it is tied to ground.

14

56F826 Technical Data

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