AP87C51FA 查看數據表（PDF） - Intel
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AP87C51FA Datasheet PDF : 18 Pages
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AUTOMOTIVE 87C51FA FB FC FC-20
AC TESTING INPUT OUTPUT WAVEFORMS
FLOAT WAVEFORMS
270961 – 17
AC Inputs during testing are driven at VCCb0 5V for a Logic ‘‘1’’
and 0 45V for a Logic ‘‘0’’ Timing measurements are made at VIH
min for a Logic ‘‘1’’ and VIL max for a Logic ‘‘0’’
270961 – 18
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs and begins to float
when a 100 mV change from the loaded VOH VOL level occurs
IOL IOH t g20 mA
Mode
Program Code Data
Verify Code Data
Program Encryption
Array Address 0–3FH
Program Lock
Bits
Bit 1
Bit 2
Bit 3
Read Signature Byte
Table 3 EPROM Programming Modes
RST
H
PSEN
L
ALE
PROG
EA
VPP
12 75V
P2 6
L
P2 7
H
H
L
H
H
L
L
H
L
12 75V L
H
H
L
H
L
H
L
H
L
12 75V H
H
12 75V H
H
12 75V H
L
H
H
L
L
P3 3
H
L
H
H
H
H
L
P3 6
H
H
L
H
L
H
L
P3 7
H
H
H
H
L
L
L
DEFINITION OF TERMS
(EPROM PROGRAMMING)
ADDRESS LINES P1 0–P1 7 P2 0–P2 5 P3 4 –
P3 5 respectively for A0–A13
DATA LINES P0 0–P0 7 for D0–D7
CONTROL SIGNALS RST PSEN P2 6 P2 7 P3 3
P3 6 P3 7
PROGRAM SIGNALS ALE PROG EA VPP
PROGRAMMING THE EPROM
The part must be running with a 4 MHz to 6 MHz
oscillator The address of an EPROM location to be
programmed is applied to address lines while the
code byte to be programmed in that location is ap-
plied to data lines Control and program signals must
be held at the levels indicated in Table 3 Normally
EA VPP is held at logic high until just before ALE
PROG is to be pulsed The EA VPP is raised to VPP
ALE PROG is pulsed low and then EA VPP is re-
turned to a high (also refer to timing diagrams)
NOTE
Exceeding the VPP maximum for any amount of
time could damage the device permanently The
VPP source must be well regulated and free of
glitches
14
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