MPC9600 查看數據表（PDF） - Integrated Device Technology

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MPC9600

Low Voltage, 2.5V and 3.3V LVCMOS PLL Clock Driver

Integrated Device Technology 

MPC9600 Data Sheet

LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER

Table 2. Function Table (Controls)

Control Pin

0

REF_SEL

VCCA

OE

CCLK

PLL Bypass(1)

Outputs Enabled

FSELA

Output Bank A at VCO/2

FSELB

Output Bank B at VCO/2

FSELC

Output Bank C at VCO/2

FSEL_FB

Feedback Output at VCO/8

1. VCCA = GND, PLL off and bypassed for static test and diagnosis.

1

PCLK

PLL Power

Outputs Disabled (except QFB)

Output Bank A at VCO/4

Output Bank B at VCO/4

Output Bank C at VCO/4

Feedback Output at VCO/12

Table 3. Absolute Maximum Ratings(1)

Symbol

Parameter

Min

Max

Unit

VCC

Supply Voltage

–0.3

4.6

V

VIN

DC Input Voltage

–0.3

VCC + 0.3

V

VOUT

DC Output Voltage

–0.3

VCC + 0.3

V

IIN

DC Input Current

20

mA

IOUT

DC Output Current

50

mA

TStor

Storage Temperature Range

–65

125

C

1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or

conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is

not implied.

Table 4. General Specifications

Symbol

Characteristics

VTT

Output Termination Voltage

MM ESD Protection (Machine Model)

HBM ESD Protection (Human Body Model)

CDM ESD Protection (Charged Device Model)

LU

Latch-Up Immunity

CPD Power Dissipation Capacitance

CIN

Input Capacitance

Min

400

4000

1500

200

Typ

VCC 2

10

4.0

Max

Unit

Condition

V

V

V

V

mA

pF Per output

pF Inputs

MPC9600 REVISION 6 JANUARY 7, 2013

4

©2013 Integrated Device Technology, Inc.

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