MPC9600 查看數據表（PDF） - Integrated Device Technology
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MPC9600 Datasheet PDF : 15 Pages
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MPC9600 Data Sheet
LOW VOLTAGE, 2.5V AND 3.3V LVCMOS PLL CLOCK DRIVER
Table 9. Typical and Maximum Period Jitter Specification
Device Configuration
All output banks in 2 or 4 divider configuration(1)
2 (FSELA = 0 and FESLB = 0 and FSELC = 0)
4 (FSELA = 1 and FESLB = 1 and FSELC = 1)
Mixed 2/4 divider configurations(2)
for output banks in 2 divider configurations
for output banks in 4 divider configurations
QA0 to QA6
Typ
Max
25
50
20
70
80
130
25
70
QB0 to QB6
Typ
Max
50
70
50
100
100
150
60
100
QC0 to QC6
Typ
Max
25
50
20
70
80
130
25
70
1. In this configuration, all MPC9600 outputs generate the same clock frequency. See Figure 3 for an example configuration.
2. Multiple frequency generation. Jitter data are specified for each output divider separately. See Figure 7 for an example.
Table 10. Typical and Maximum Cycle-to-Cycle Jitter Specification
Device Configuration
All output banks in 2 or 4 divider configuration(1)
2 (FSELA = 0 and FESLB = 0 and FSELC = 0)
4 (FSELA = 1 and FESLB = 1 and FSELC = 1)
Mixed 2/ 4 divider configurations(2)
for output banks in 2 divider configurations
for output banks in 4 divider configurations
QA0 to QA6
Typ
Max
40
90
40
110
150
250
30
110
QB0 to QB6
Typ
Max
80
130
120
180
200
280
120
180
1. In this configuration, all MPC9600 outputs generate the same clock frequency.
2. Multiple frequency generation. Jitter data are specified for each output divider separately.
QC0 to QC6
Typ
Max
40
90
40
110
150
250
30
110
fref = 20.833 MHz
1
0
0
0
CCLK
QA0–6
FB_IN
FSEL_FB
QB0–6
QC0–6
FSELA
FSELB
QFB
FSELC
MPC9600
20.833 MHz (Feedback)
125 MHz
7
125 MHz
7
125 MHz
7
Frequency Range
Input
QA outputs
QB outputs
QC outputs
Min
16.67 MHz
100 MHz
100 MHz
100 MHz
Max
33.33 MHz
200 MHz
200 MHz
200 MHz
Figure 3. Configuration for 126 MHz Clocks
fref = 33.33 MHz
0
0
1
1
CCLK
QA0–6
FB_IN
FSEL_FB
QB0–6
QC0–6
FSELA
FSELB
QFB
FSELC
MPC9600
33.33 MHz (Feedback)
133.3 MHz
7
66.67 MHz
7
66.67 MHz
7
Frequency Range
Input
QA outputs
QB outputs
QC outputs
Min
25 MHz
100 MHz
100 MHz
100 MHz
Max
50 MHz
200 MHz
200 MHz
200 MHz
Figure 4. Configuration for 133.3/66.67 MHz Clocks
MPC9600 REVISION 6 JANUARY 7, 2013
8
©2013 Integrated Device Technology, Inc.
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