MC12430
SCLOCK
FREF
MCNT
PLL 12430
M COUNTER
VCO_CLK
0
1
SEL_CLK
SDATA SHIFT
REG
14–BIT T0
T1
T2
LATCH
SLOAD
Reset
PLOADB
DECODE
N DIVIDE
(1, 2, 4, 8)
FOUT
(VIA ENABLE GATE)
FDIV4
MCNT
LOW
FOUT
MCNT
FREF
HIGH
7
TEST
MUX
0
TEST
• T2=T1=1, T0=0: Test Mode
• SCLOCK is selected, MCNT is on TEST output, SCLOCK DIVIDE BY N is on FOUT pin
PLOADB acts as reset for test pin latch. When latch reset T2 data is shifted out TEST pin.
Figure 2. Serial Test Clock Block Diagram
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V to 5.0V ±5%)
Symbol
Characteristic
Min
Typ
VIH
Input HIGH Voltage
2.0
VIL
Input LOW Voltage
IIN
Input Current
VOH
Output HIGH Voltage
2.17
VOL
Output LOW Voltage
1.41
ICC
Power Supply Current
VCC
85
PLL_VCC
15
1. Output levels will vary 1:1 with VCC0 variation.
Max
Unit
Condition
V
VCC = 3.3 to 5.0V
0.8
V
VCC = 3.3 to 5.0V
1.0
mA
2.50
V
VCC0 = 3.3V1
1.76
V
VCC0 = 3.3V1
100
mA
20
TIMING SOLUTIONS
5
BR1333 — Rev 6
MOTOROLA