BUK128-50DL 查看數據表（PDF） - Philips Electronics
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BUK128-50DL Datasheet PDF : 6 Pages
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Philips Semiconductors
Logic level TOPFET
SMD version of BUK117-50DL
Product specification
BUK128-50DL
INPUT CHARACTERISTICS
The supply for the logic and overload protection is taken from the input.
Limits are for -40˚C ≤ Tmb ≤ 150˚C; typicals are for Tmb = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN.
VIS(TO)
IIS
IISL
VISR
tlr
V(CL)IS
RIG
Input threshold voltage
Input supply current
Input supply current
Protection reset voltage1
Latch reset time
Input clamping voltage
Input series resistance2
to gate of power MOSFET
VDS = 5 V; ID = 1 mA
0.6
Tmb = 25˚C 1.1
normal operation;
VIS = 5 V
100
VIS = 4 V
80
protection latched;
VIS = 5 V
200
VIS = 3 V
130
reset time tr ≥ 100 µs
1.5
VIS1 = 5 V, VIS2 < 1 V
10
II = 1.5 mA
5.5
Tmb = 25˚C
-
TYP.
-
1.6
220
195
400
250
2
40
-
33
MAX. UNIT
2.4 V
2.1 V
400 µA
330 µA
650 µA
430 µA
2.9 V
100 µs
8.5 V
-
kΩ
SWITCHING CHARACTERISTICS
Tmb = 25 ˚C; VDD = 13 V; resistive load RL = 4 Ω. Refer to waveform figure and test circuit.
SYMBOL PARAMETER
CONDITIONS
MIN.
td on
Turn-on delay time
VIS = 5 V
-
tr
Rise time
-
td off
Turn-off delay time
VIS = 0 V
-
tf
Fall time
-
TYP.
8
20
25
16
MAX. UNIT
20 µs
50 µs
70 µs
40 µs
1 The input voltage below which the overload protection circuits will be reset.
2 Not directly measureable from device terminals.
May 2001
4
Rev 1.800
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