TX4925 查看數據表（PDF） - Toshiba
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TX4925 Datasheet PDF : 32 Pages
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INTEGRATED CIRCUIT
TOSHIBA RISC PROCESSOR
TMPR4925XB
TENTATIVE
Signal Name
ID_SEL
DEVSEL*
REQ [3:2] *
REQ [1] *
REQ [0] *
GNT [3:0] *
PERR*
SERR*
Type
Input
Input/out
put
Input
Input/out
put/OD
Input/out
put
Input/out
put
Input/out
put
Input/OD
Function
Initial State
Initialization Device Select
Chip select signal used for configuration access.
Input
Device Select
The target asserts this signal in response to access from the initiator.
Input
Request
Signals used by the master to request bus mastership.
The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI
bus arbiter is used.
In internal arbiter mode, REQ[3:2]* are PCI bus request input signals.
In external arbiter mode, REQ[3:2]* are not used. Because the pins are still placed
in the input state, they must be pulled up externally.
Input
Request
Signal used by the master to request bus mastership.
The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI
bus arbiter is used.
In internal arbiter mode, this signal is a PCI bus request input signal.
In external arbiter mode, this signal is an external interrupt output signal (INTOUT).
Selected
by
ADDR[1]
H: Input
L: Hi-Z
Request
Signal used by the master to request bus mastership.
The boot configuration signal on the ADDR[1] pin determines whether the built-in PCI
bus arbiter is used.
In internal arbiter mode, this signal is a PCI bus request input signal.
In external arbiter mode, this signal is a PCI bus request output signal.
Selected
by
ADDR[1]
H: Input
L: High
Grant
Indicates that bus mastership has been granted to the PCI bus master.
The boot configuration signal on the ADDR[1] pin determines whether the built-in
PCI bus arbiter is used.
In internal arbiter mode, all of GNT[3:0]* are PCI bus grant output signals.
In external arbiter mode, GNT[0]* is a PCI bus grant input signal. Because GNT[3:1]*
also become input signals, they must be pulled up externally.
Selected
by
ADDR[1]
H: All High
L: Input
Data Parity Error
Input
Indicates a data parity error in a bus cycle other than special cycles.
System Error
Indicates an address parity error, a data parity error in a special cycle, or a fatal
error.
In host mode, SERR* is an input signal. In satellite mode, SERR* is an open-drain
output signal. The mode is determined by the boot configuration signal on the
ADDR[19] pin.
Input
EJC-TMPR4925XB -20
26/Dec/01 Rev 0.1
TOSHIBA CORPORATION
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