TSL26727 查看數據表（PDF） - austriamicrosystems AG
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TSL26727 Datasheet PDF : 31 Pages
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TSL2672
DIGITAL PROXIMITY DETECTOR
TAOS133 − MAY 2012
Wait Characteristics, VDD = 3 V, TA = 255C, WEN = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
CHANNEL
MIN TYP
Wait step size
WTIME = 0xFF
2.58 2.73
Wait number of integration steps (Note 1)
1
NOTE 1: Parameter ensured by design and is not tested.
MAX
2.9
256
UNIT
ms
steps
AC Electrical Characteristics, VDD = 3 V, TA = 255C (unless otherwise noted)
PARAMETER†
TEST CONDITIONS
MIN
lid f(SCL)
Clock frequency (I2C only)
0
t(BUF)
Bus free time between start and stop condition
1.3
Hold time after (repeated) start condition. After
a t(HDSTA)
this period, the first clock is generated.
0.6
t(SUSTA)
Repeated start condition setup time
0.6
v t(SUSTO)
Stop condition setup time
0.6
ill t(HDDAT)
Data hold time
0
t(SUDAT)
Data setup time
100
t(LOW)
SCL clock low period
1.3
t t(HIGH)
SCL clock high period
0.6
G s tF
Clock/data fall time
tR
Clock/data rise time
A t Ci
Input pin capacitance
s n † Specified by design and characterization; not production tested.
TYP MAX UNIT
400 kHz
μs
μs
μs
μs
μs
ns
μs
μs
300 ns
300 ns
10 pF
am nte PARAMETER MEASUREMENT INFORMATION
o SCL
l c t(BUF)
ica SDA
t(LOW)
t(R)
VIH
VIL
t(HDSTA)
t(HDDAT)
VIH
VIL
t(F)
t(HIGH) t(SUSTA)
t(SUDAT)
P
Stop
Techn Condition
S
Start
Condition
S
Figure 1. Timing Diagrams
t(SUSTO)
P
Copyright E 2012, TAOS Inc.
6
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www.taosinc.com
The LUMENOLOGY r Company
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