VV5430 查看數據表（PDF） - STMicroelectronics

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VV5430

Monochrome Analog Output CMOS Image Sensors

STMicroelectronics 

VV5430

Serial Communication

stop start

SDA

start stop

...

Tbuf

Tlo Tr

SCL

Tf

...

Thd;sta

Thd;sta

Thd;dat Thi Tsu;dat

Tsu;sta

Tsu;sto

Note: All values referred to the minimum input level (high) = 3.5V, and maximum input level (low) = 1.5V

Parameter

Symbol

Min.

Max.

Unit

SCL clock frequency

Fscl

0

100

kHz

Bus free time between a

Tbuf

4.7

-

µs

stop and a start

Hold time for a repeated

Thd;sta

4.0

-

µs

start

LOW period of SCL

Tlo

4.7

-

µs

HIGH period of SCL

Thi

4.0

-

µs

Set-up time for a repeated

Tsu;sta

4.7

-

µs

start

Data hold time

Thd;dat

01

-

µs

Data Set-up time

Tsu;dat

250

-

ns

Rise time of SCL, SDA

Tr

-

1000

ns

Fall time of SCL, SDA

Tf

-

300

ns

Set-up time for a stop

Tsu;sto

4.0

-

µs

Capacitive load of each

Cb

bus line (SCL, SDA)

-

100

pF

1. The VV5430 internally provides a hold time of at least 300ns for the SDA signal (referred

to the minimum input level (high) of the SCL signal) to bridge the undefined region of the

falling edge of SCL

Table 13 : Serial Interface Timing Characteristics

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CD5430F-A

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