LH28F008SC 查看數據表（PDF） - Sharp Electronics

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LH28F008SC

8M (1M × 8) Flash Memory

Sharp Electronics 

LH28F008SC

8M (1M × 8) Flash Memory

Set Block and Master

Lock-Bit Commands

A flexible block locking and unlocking scheme is

enabled via a combination of block lock-bits and a mas-

ter lock-bit. The block lock-bits gate program and erase

operations while the master lock-bit gates block-lock bit

modification. With the master lock-bit not set, individual

block lock-bits can be set using the Set Block Lock-Bit

command. The Set Master Lock-Bit command, in con-

junction with RP » = VHH, sets the master lock-bit. After

the master lock-bit is set, subsequent setting of block

lock-bits requires both the Set Block Lock-Bit command

and VHH on the RP » pin. See Write Protection Analysis

Table for a summary of hardware and software write

protection options.

Set block lock-bit and master lock-bit are executed

by a two-cycle command sequence. The set block or

master lock-bit setup along with appropriate block or

device address is written followed by either the set block

lock-bit confirm (and an address within the block to be

locked) or the set master lock-bit confirm (and any

device address). The WSM then controls the set lock-

bit algorithm. After the sequence is written, the device

automatically outputs status register data when read

(see Figure 10). The CPU can detect the completion of

the set lock-bit event by analyzing the RY »/BY » pin out-

put or status register bit SR.7.

When the set lock-bit operation is complete, status

register, bit SR.4 should be checked. If an error is

detected, the status register should be cleared. The CUI

will remain in read status register mode until a new com-

mand is issued.

This two-step sequence of set-up followed by execu-

tion ensures that lock-bits are not accidentally set. An

invalid Set Block or Master Lock-Bit command will

result in status register bits SR.4 and SR.5 being set

to '1'. Also, reliable operations occur only when

VCC = VCC1/2/3 and VPP = VPPH1/2/3. In the absence of

this high voltage, lock-bit contents are protected against

alteration.

A successful set block lock-bit operation requires that

the master lock-bit be cleared or, if the master lock-bit

is set, that RP » = VHH. If it is attempted with the master

lock-bit set and RP » = VIH, SR.1 and SR.4 will be set to

'1' and the operation will fail. Set block lock-bit opera-

tions while VIH < RP » < VHH produce spurious results

and should not be attempted. A successful set master

lock-bit operation requires that RP » = VHH. If it is at-

tempted with RP » = VIH, SR.1 and SR.4 will be set to '1'

and the operation will fail. Set master lock-bit opera-

tions withVIH < RP » < VHH produce spurious results and

should not be attempted.

Clear Block Lock-Bits Command

All set block lock-bits are cleared in parallel via the

Clear Block Lock-Bits command. With the master lock-

bit not set, block lock-bits can be cleared using only the

Clear Block Lock-Bits command. If the master lock-bit

is set, clearing block lock-bits requires both the Clear

Block Lock-Bits command and VHH on the RP » pin. See

Write Protection Analysis Table for a summary of hard-

ware and software white protection options.

Clear block lock-bits operation is executed by a two-

cycle command sequence. A clear block lock-bits setup

is first written. After the command is written, the device

automatically outputs status register data when read

(see Figure 11). The CPU can detect completion of the

clear block lock-bits event by analyzing the RY »/BY » Pin

output or status register bit SR.7.

When the operation is complete, status register bit

SR.5 should be checked. If a clear block lock-bit error is

detected, the status register should be cleared. The CUI

will remain in read status register mode until another

command is issued.

This two-step sequence of set-up followed by execu-

tion ensures that block lock-bits are not accidentally

cleared. An invalid Clear Block Lock-Bits command

sequence will result in status register bits SR.4 and SR.5

being set to “1”. Also, a reliable clear block lock bits

operation can only occur when VCC = VCC1/2/3 and

VPP = VPPH1/2/3. If a clear block lock-bits operation is

attempted whileVPP ≤ VPPLK, SR.3 and SR.5 will be set

to '1'. In the absence of this high voltage, the block lock-

bits content are protected against alteration. A success-

ful clear block lock-bits operation requires that the master

lock-bit is not set or, if the master lock-bit is set, that

RP » = VHH. If it is attempted with the master lock-bit set

and RP » = VIH, SR.1 and SR.5 will be set to '1' and the

operation will fail. A clear block lock-bits operation with

VIH < RP » < VHH produce spurious results and should

not be attempted.

If a clear block lock-bits operation is aborted due to

VPP or VCC transitioning out of valid range or RP »

active transition, block lock-bit values are left in an

undetermined state. A repeat of clear block lock-bits is

required to initialize block lock-bit contents to known

value. Once the master lock-bit is set, it cannont be

cleared.

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