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ADSP-BF527C(RevPrC) 查看數據表(PDF) - Analog Devices

零件编号
产品描述 (功能)
生产厂家
ADSP-BF527C
(Rev.:RevPrC)
ADI
Analog Devices ADI
ADSP-BF527C Datasheet PDF : 44 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
Preliminary Technical Data
ADSP-BF523C/ADSP-BF525C/ADSP-BF527C
MASTER AND SLAVE MODE OPERATION
The CODEC can be configured as either a master or slave mode
device. As a master mode device the CODEC controls sequenc-
ing of the data and clocks on the digital audio interface. As a
slave device the CODEC responds with data to the clocks it
receives over the digital audio interface. The mode is set with
the MS bit of the control register as shown in Table 15.
Table 15. Programming Master/Slave Modes
Register Bit Label Default Description
Address
000 0111 6 MS 0
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
As a master mode device the CODEC controls the sequencing of
data transfer (ADCDAT, DACDAT) and output of clocks
(CODEC_BCLK, ADCLRC, DACLRC) over the digital audio
interface. It uses the timing generated from either its on-board
crystal or the CODEC_MCLK input as the reference for the
clock and data transitions. This is illustrated in Figure 24. ADC-
DAT is always an output from the CODEC and DACDAT is
always an input to the CODEC whether in master or slave
mode.
As a slave device the CODEC sequences the data transfer
(ADCDAT, DACDAT) over the digital audio interface in
response to the external applied clocks (CODEC_BCLK,
ADCLRC, DACLRC). This is illustrated in Figure 25.
The CODEC relies on controlled phase relationships between
audio interface CODEC_BCLK, DACLRC and the master
CODEC_MCLK or CODEC_CLKOUT. To avoid timing haz-
ards, see CODEC Clock Timing on Page 34 for detailed
information.
CODEC_BCLK
CODEC
ADCLRC
DACLRC
ADCDAT
DACDAT
TSCLKx/RSCLKx
TFSx
RFSx
BLACKFIN
DRxPRI/DRxSEC
DTxPRI/DTxSEC
NOTE: ADC AND DAC CAN RUN AT DIFFERENT RATES
Figure 24. Master Mode
CODEC_BCLK
TSCLKx/RSCLKx
CODEC
ADCLRC
DACLRC
ADCDAT
DACDAT
TFSx
RFSx
BLACKFIN
DRxPRI/DRxSEC
DTxPRI/DTxSEC
OTE: ADC AND DAC CAN RUN AT DIFFERENT RATES
Figure 25. Slave Mode
AUDIO DATA SAMPLING RATES
The CODEC provides for two modes of operation (normal and
USB) to generate the required DAC and ADC sampling rates.
Use Table 16 to program normal and USB modes.
Table 16. Sample Rate Control
Register Bit Label Default Description
Address
0001000 0 USB/ 0
NORMAL
1 BOSR 0
Mode Select
1 = USB mode (250/272 × fS)
0 = Normal mode (256/384 × fS)
Base Over-Sampling Rate
5:2 SR[3:0] 0000
USB Mode
0 = 250 × fS
1 = 272 × fS
Normal Mode 96/88.2 kHz
0 = 256 × fS
0 = 128 × fS
1 = 384 × fS
1 = 192 × fS
ADC and DAC sample rate control
(see Normal Mode Sample Rates
and USB Mode Sample Rates on
Page 23)
In normal mode, the user controls the sample rate by using an
appropriate CODEC_MCLK or crystal frequency and the sam-
ple rate control register setting. The CODEC can support
sample rates from 8K samples/s up to 96K samples/s.
In USB mode, a fixed CODEC_MCLK or crystal frequency of 12
MHz is used to generate sample rates from 8K samples/s to
96K samples/s. It is called USB mode since the common USB
clock is 12 MHz. The CODEC can generate all the normal audio
sample rates from this one master clock, without the need for
different master clocks or PLL circuits.
The CODEC offers the user the ability to sample the ADC and
DAC at different rates under software control in both normal
and USB modes. This reduces the burden on a controlling pro-
cessor. However, signal processing in the ADC and DAC over-
sampling filters is tightly coupled to minimize power consump-
tion. For that reason, only the combinations of sample rates
listed in the following sections are supported. These rates are
expected to be the combinations used in typical audio systems.
Normal Mode Sample Rates
In normal mode, the CODEC_MCLK/crystal oscillator is set up
according to the desired sample rates of the ADC and DAC. For
ADC or DAC sampling rates of 8, 32, 48 or 96 kHz,
CODEC_MCLK frequencies of either 12.288 MHz (256 × fS) or
18.432 MHz (384 × fS) can be used. For ADC or DAC sampling
rates of 8, 44.1 or 88.2 kHz—CODEC_MCLK frequencies of
either 11.2896 MHz (256 × fS) or 16.9344 MHz (384 × fS) can be
used.
Table 17 can be used to set up the device for various sample rate
combinations. For example if the user wishes to use the CODEC
in normal mode with the ADC and DAC sample rates at 48 kHz
Rev. PrC | Page 21 of 44 | June 2008

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