ADSP-BF527KBCZ-6C2 查看數據表（PDF） - Analog Devices

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ADSP-BF527KBCZ-6C2

Blackfin Embedded Processor with Codec

Analog Devices 

ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C

BIT DESCRIPTIONS

Table 4 through Table 14 on Page 20 describe each bit in the

control registers.

Table 4. Register 0 Left-Channel ADC Input Volume

Bit Name Bits Description

LRINBOTH B8

Left-to-right line input ADC

data load control

LINMUTE

B7

Left-channel input mute

LINVOL

B[5:0] Left-channel PGA volume control

Settings

0 = disable simultaneous loading of left-channel

ADC data to right-channel register (default)

1 = enable simultaneous loading of left-channel

ADC data to right-channel register

0 = disable mute

1 = enable mute on data path to ADC (default)

00 0000 = –34.5 dB

… 1.5 dB step up

01 0111 = 0 dB (default)

… 1.5 dB step up

01 1111 = 12 dB

10 0000 = 13.5 dB

10 0001 = 15 dB

10 0010 = 16.5 dB

10 0011 = 18 dB

10 0100 = 19.5 dB

10 0101 = 21 dB

10 0110 = 22.5 dB

10 0111 = 24 dB

10 1000 = 25.5 dB

10 1001 = 27 dB

10 1010 = 28.5 dB

10 1011 = 30 dB

10 1100 = 31.5 dB

10 1101 = 33 dB

11 1111 to 10 1101 = 33 dB

Rev. A | Page 16 of 36 | March 2010

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