ADSP-BF523KBCZ-6C2 查看數據表（PDF） - Analog Devices

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ADSP-BF523KBCZ-6C2

Blackfin Embedded Processor with Codec

Analog Devices 

ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C

Table 5. Register 1 Right-Channel ADC Input Volume

Bit Name Bits Description

RLINBOTH B8

Right-to-left line input ADC

data load control

RINMUTE B7 Right-channel input mute

RINVOL

B[5:0] Right-channel PGA volume control

Table 6. Register 2 Left-Channel DAC Volume

Bit Name Bits

LRHPBOTH B8

Description

Left-to-right headphone volume

load control

LZCEN

LHPVOL

B7 Left-channel zero cross detect enable

B[6:0] Left-channel headphone volume control

Settings

0 = disable simultaneous loading of right-channel

ADC data to left-channel register (default)

1 = enable simultaneous loading of right-channel

ADC data to left-channel register

0 = disable mute

1 = enable mute on data path to ADC (default)

00 0000 = –34.5 dB

… 1.5 dB step up

01 0111 = 0 dB (default)

… 1.5 dB step up

01 1111 = 12 dB

10 0000 = 13.5 dB

10 0001 = 15 dB

10 0010 = 16.5 dB

10 0011 = 18 dB

10 0100 = 19.5 dB

10 0101 = 21 dB

10 0110 = 22.5 dB

10 0111 = 24 dB

10 1000 = 25.5 dB

10 1001 = 27 dB

10 1010 = 28.5 dB

10 1011 = 30 dB

10 1100 = 31.5 dB

10 1101 = 33 dB

11 1111 to 10 1101 = 33 dB

Settings

0 = disable simultaneous loading of left-channel

headphone volume data to right-channel register (default)

1 = enable simultaneous loading of left-channel

headphone volume data to right-channel register

0 = disable (default)

1 = enable

000 0000 to 010 1111 = mute

011 0000 = –73 dB

…

111 1001 = 0 dB (default)

… 1 dB steps up to

111 1111 = +6 dB

Rev. A | Page 17 of 36 | March 2010

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