ADSP-BF525KBCZ-5C2 查看數據表（PDF） - Analog Devices

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ADSP-BF525KBCZ-5C2

Blackfin Embedded Processor with Codec

Analog Devices 

ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C

Table 9. Register 5 Digital Audio Path

Bit Name

HPOR

Bits Description

B4 Store dc offset when high-pass filter is disabled

DACMU

B3 DAC digital mute

DEEMPH[1:0] B[2:1] De-emphasis control

ADCHPD

B0 ADC high-pass filter control

Table 10. Register 6 Power Management

Bit Name

POWEROFF

Bits Description

B7 Whole chip power-down control

CLKOUTPD

B6 Clock output power-down control

OSCPD

B5 Crystal power-down control

OUTPD

B4 Output power-down control

DACPD

B3 DAC power-down control

ADCPD

B2 ADC power-down control

MICPD

B1 Microphone input power-down control

LINEINPD

B0 Line input power-down control

Settings

0 = clear offset (default)

1 = store offset

0 = no mute (signal active)

1 = mute (default)

00 = no de-emphasis (default)

01 = 32 kHz sampling rate

10 = 44.1 kHz sampling rate

11 = 48 kHz sampling rate

0 = ADC high-pass filter enable (default)

1 = ADC high-pass filter disable

Settings

0 = power-up

1 = power-down (default)

0 = power-up (default)

1 = power-down

0 = power-up (default)

1 = power-down

0 = power-up

1 = power-down (default)

0 = power-up

1 = power-down (default)

0 = power-up

1 = power-down (default)

0 = power-up

1 = power-down (default)

0 = power-up

1 = power-down (default)

Rev. A | Page 19 of 36 | March 2010

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