ADSP-21368SKBPZENG 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

ADSP-21368SKBPZENG

SHARC® Processor

Analog Devices 

ADSP-21368

Preliminary Technical Data

Reset

Table 10. Reset

Parameter

Min

Max

Unit

Timing Requirements

tWRST1

RESET Pulse Width Low

4tCK

ns

tSRST

RESET Setup Before CLKIN Low

8

ns

1 Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming

stable VDD and CLKIN (not including start-up time of external clock oscillator).

CLKIN

RESET

tWRST

Figure 7. Reset

Interrupts

The following timing specification applies to the FLAG0,

FLAG1, and FLAG2 pins when they are configured as IRQ0,

IRQ1, and IRQ2 interrupts.

Table 11. Interrupts

Parameter

Timing Requirement

tIPW

IRQx Pulse Width

tSRST

Min

2 × tPCLK +2

Max

DPI14-1

FLAG2-0

(IRQ2-0)

tIPW

Figure 8. Interrupts

Unit

ns

Rev. PrA | Page 20 of 48 | November 2004

Share Link: