1EDF5673KXUMA1 查看數據表（PDF） - Infineon Technologies
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1EDF5673KXUMA1 Datasheet PDF : 39 Pages
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1EDF5673K, 1EDF5673F, 1EDS5663H
GaN gate driver
Timing diagrams
5
Timing diagrams
Figure 7 depicts rise, fall and delay times as observed at the capacitively loaded outputs OUTS and OUTG, resp.
As OUTG is not actively switched to low, a resistor in parallel with the load capacitance has to be used for testing.
In addition to the signal propagation delay tPDon, the rising edge of OUTG is delayed by a time t1 defining the
duration of negative VGS.
PWM
VINH
VINL
OUTS
10%
tPDonS
90%
tPDoffS
Figure 7
OUTG
10%
t1
tPDoffG
Propagation delay, rise and fall time
90%
10%
trise
tfall
90%
10%
trise
Figure 8 illustrates a complete switching sequence of the four switches forming the two output stages of
GaN EiceDRIVER™ (delay, rise and fall times not shown). The sequence in the left part of Figure 8 corresponds to
the normal switching operation, whereas in the right part the "first pulse" situation is depicted. This situation is
assumed to happen whenever there is no switching action for an extended period t2. Clearly t2 must be
significantly longer than a regular switching period. A typical duration of 32 µs has been chosen, as GaN switches
usually operate at switching frequencies significantly above 50 kHz (switching period below 20 µs).
normal operation
on
off
PWM
on
off S1
S2
t2 >> 1/fsw
“first pulse“
S3
t1
t3
S4
Figure 8
VGS
-VN
-VDDO
Input signal, output switch sequence and resulting VGS for normal operation and
"first pulse" situation
Final datasheet
18
Rev. 2.3
2020-10-22
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