LTC692C 查看數據表（PDF） - Linear Technology

零件编号

产品描述 (功能)

生产厂家

LTC692C

Microprocessor Supervisory Circuits

Linear Technology 

LTC692/LTC693

APPLICATIONS INFORMATION

Example 2: The circuit in Figure 9 can be used to measure

the regulated 5V supply to provide early warning of power

failure. Because of variations in the PFI threshold, this

circuit requires adjustment to ensure the PFI comparator

trips before the reset threshold is reached. Adjust R5 such

that the PFO output goes low when the VCC supply reaches

the desired level (e.g., 4.6V).

Monitoring the Status of the Battery

C3 can also monitor the status of the memory backup

battery (Figure 10). If desired, the CE OUT can be used to

apply a test load to the battery. Since CE OUT is forced high

in battery backup mode, the test load will not be applied

to the battery while it is in use, even if the microprocessor

is not powered.

5V

VBATT VCC

PFO

LOW-BATTERY SIGNAL

3V

R1

TO μP I/O PIN

1M

PFI LTC693

R2

1M

CE IN

I/O PIN

CE OUT GND

RL

20K

692_3 • F10

OPTIONAL TEST LOAD

Watchdog Timer

The LTC692/LTC693 provide a watchdog timer function to

monitor the activity of the microprocessor. If the micropro-

cessor does not toggle the watchdog input (WDI) within

a seleced time-out period, RESET is forced to active low

for a minimum of 140ms. The reset active time is adjust-

able on the LTC693. Since many systems cannot service

the watchdog timer immediately after a reset, the LTC693

has longer time-out period (1.0 second minimum) right

after a reset is issued. The normal time-out period (70ms

minimum) becomes effective following the first transition

of WDI after RESET is inactive. The watchdog time-out

period is fixed at a 1.0 second minimum on the LTC692.

Figure 11 shows the timing diagram of watchdog time-out

period and reset active time. The watchdog time-out period

is restarted as soon as RESET is inactive. When either a

high-to-low or low-to-high transition occurs at the WDI pin

prior to time-out, the watchdog timer is reset and begins

to time-out again. To ensure the watchdog timer does not

time-out, either a high-to-low or low-to-high transition

on the WDI pin must occur at or less than the minimum

time-out period. If the input to the WDI pin remains either

high or low, reset pulses will be issued every 1.6 seconds

typically. The watchdog timer can be deactivated by float-

ing the WDI pin. The timer is also disabled when VCC falls

below the reset voltage threshold or VBATT.

Figure 10. Backup Battery Monitor with Optional Test Load

VCC = 5V

WDI

WDO

RESET

t1 = RESET ACTIVE TIME

t2 = NORMAL WATCHDOG TIME-OUT PERIOD

t3 = WATCHDOG TIME-OUT PERIOD IMMEDIATELY

AFTER A RESET

t2

t3

t1

t1

692_3 • F11

Figure 11. Watchdog Time-Out Period and Reset Active Time

0692fa

14

Share Link: