M66252P 查看數據表（PDF） - MITSUBISHI ELECTRIC

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M66252P

1152 x 8-BIT LINE MEMORY (FIFO)

MITSUBISHI ELECTRIC  

MITSUBISHI 〈DIGITAL ASSP〉

M66252P/FP

1152 x 8-BIT LINE MEMORY (FIFO)

VARIABLE-LENGTH DELAY BITS

• 1-line (1152-bit) delay

A write input data is written into memory at the second rise edge of WCK in the cycle, and a read output data is output from

memory at the first rise edge of RCK in the cycle, so that 1-line delay can be made easily.

WCK

RCK

Cycle 0 Cycle 1 Cycle 2

tRESS tRESH

WRES

RRES

tDS tDH

Dn

(0)

(1)

(2)

Cycle

1150

Cycle

1151 Cycle 0’ Cycle 1’ Cycle 2’

tDS tDH

(1149) (1150) (1151)

(0’)

(1’)

(2’)

1152 cycles

tAC

tOH

Qn

(0)

(1)

(2)

WE, RE=“L”

• n-bit delay 1

(Making a reset at a cycle corresponding to delay length)

Cycle 0 Cycle 1 Cycle 2

Cycle

(n–2)

WCK

RCK

tRESS tRESH

WRES

RRES

tDS tDH

Cycle

(n–1) Cycle 0’ Cycle 1’ Cycle 2’ Cycle 3’

tRESS tRESH

tDS tDH

Dn

(0)

(1)

(2)

(n–3) (n–2) (n–1)

(0’)

(1’)

(2’)

(3’)

m cycles

tAC

tOH

Qn

(0)

(1)

(2)

(3)

WE, RE=“L”

m≥3

8

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