Philips Semiconductors
Frequency Shift Keying (FSK) receiver
Preliminary specification
UAA3202M
handbook, full pagewidth
VPWD
(V)
3.5
0
0
MHA834
100
200
300
400
500 t (ms)
Fig.5 Timing diagram for pulsed power-down voltage.
GENERATOR 1
50 Ω
TEST CIRCUIT (1)
BER TEST
FACILITY (2)
MED900
(1) For test circuit see Fig.11.
(2) For BER test facility see Fig.10.
Fig.6 Test configuration A (single generator).
GENERATOR 1
50 Ω
GENERATOR 2
50 Ω
(1) For test circuit see Fig.11.
1997 Aug 12
50 Ω
2-SIGNAL
POWER
COMBINER
TEST CIRCUIT (1)
SPECTRUM
ANALYZER
WITH
PROBE
IM3
∆f
∆f
∆f
∆f = 100 kHz
MED901
Fig.7 Test configuration B (IP3).
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