SN74LS273ML2 查看數據表（PDF） - ON Semiconductor
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SN74LS273ML2 Datasheet PDF : 8 Pages
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SN74LS273
FUNCTIONAL DESCRIPTION
The SN74LS273 is an 8-Bit Parallel Register with a
common Clock and common Master Reset.
When the MR input is LOW, the Q outputs are LOW,
independent of the other inputs. Information meeting the
setup and hold time requirements of the D inputs is
transferred to the Q outputs on the LOW-to-HIGH transition
of the clock input.
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min Typ Max Unit
Test Conditions
VIH
Input HIGH Voltage
2.0
V
Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
VIK
VOH
Input Clamp Diode Voltage
Output HIGH Voltage
–0.65 –1.5
V
VCC = MIN, IIN = –18 mA
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VOL
Output LOW Voltage
0.25 0.4
V
0.35 0.5
V
IIH
Input HIGH Current
20
µA
0.1
mA
IIL
Input LOW Current
–0.4 mA
IOS
Short Circuit Current (Note 2.)
–20
–100 mA
ICC
Power Supply Current
27
mA
2. Not more than one output should be shorted at a time, nor for more than 1 second.
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
VCC = MAX, VIN = 0.4 V
VCC = MAX
VCC = MAX
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max
fMAX
Maximum Input Clock Frequency
30
40
tPHL
Propagation Delay, MR to Q Output
18
27
tPLH
tPHL
Propagation Delay, Clock to Output
17
27
18
27
Unit
MHz
ns
ns
Test Conditions
Figure 1
Figure 2
Figure 1
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max Unit
tw
Pulse Width, Clock or Clear
20
ns
ts
Data Setup Time
20
ns
th
Hold Time
5.0
ns
trec
Recovery Time
25
ns
Test Conditions
Figure 1
Figure 1
Figure 1
Figure 2
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