SL74HCT273N 查看數據表（PDF） - System Logic Semiconductor
零件编号
产品描述 (功能)
生产厂家
SL74HCT273N Datasheet PDF : 5 Pages
| |||
SL74HCT273
AC ELECTRICAL CHARACTERISTICS(VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Symbol
fmax
tPLH, tPHL
tPHL
tTLH, tTHL
CIN
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Maximum Propagation Delay, Clock to Q (Figures
1 and 4)
Maximum Propagation Delay , Reset to Q (Figures
2 and 4)
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Maximum Input Capacitance
Guaranteed Limit
25 °C to ≤85°C ≤125°C
-55°C
30
24
20
25
28
35
25
28
35
18
20
22
10
10
10
Unit
MHz
ns
ns
ns
pF
Power Dis sipation Capacitance (Per Gate)
CPD Used to determine the no-load dynamic power
consumption:
PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
30
pF
TIMING REQUIREMENTS (VCC =5.0 V ± 10%, CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25 °C to
-55°C
≤85°C
≤125°C
Unit
tSU
Minimum Setup Time, Data to
10
12
15
ns
Clock (Figure 3)
th
Minimum Hold Time, Clock to
3.0
3.0
3.0
ns
Data (Figure 3)
trec
Minimum Recovery Time,
5.0
5.0
5.0
ns
Reset Inactive to Clock (Figure
2)
tw
Minimum Pulse Width, Clock
12
15
18
ns
(Figure 1)
tw
Minimum Pulse Width, Reset
12
15
18
ns
(Figure 2)
tr, tf Maximum Input Rise and Fall
500
500
500
ns
Times (Figure 1)
SLS
System Logic
Semiconductor
Share Link: 