74LV374DB 查看數據表（PDF） - Philips Electronics
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74LV374DB Datasheet PDF : 12 Pages
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Philips Semiconductors
Octal D-type flip-flop; positive edge-trigger (3-State)
Product specification
74LV374
FEATURES
• Wide operating voltage: 1.0 to 5.5V
• Optimized for Low Voltage applications: 1.0 to 3.6V
• Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V
• Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V,
Tamb = 25°C
• Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V,
Tamb = 25°C
• Common 3-State output enable input
• Output capability: bus driver
• ICC category: MSI
DESCRIPTION
The 74LV374 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT374.
The 74LV374 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented
applications. A clock (CP) and an output enable (OE) input are
common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition.
When OE is LOW, the contents of the eight flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf v2.5 ns
SYMBOL
PARAMETER
tPHL/tPLH
Propagation delay
CP to Qn
CONDITIONS
CL = 15pF
VCC = 3.3V
fmax
Maximum clock frequency
CI
Input capacitance
CPD
Power dissipation capacitance per flip-flop Notes 1 and 2
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD VCC2 x fi )S (CL VCC2 fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL VCC2 fo) = sum of the outputs.
2. The condition is VI = GND to VCC
TYPICAL
14
77
3.5
25
ORDERING INFORMATION
PACKAGES
20-Pin Plastic DIL
20-Pin Plastic SO
20-Pin Plastic SSOP Type II
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LV374 N
74LV374 D
74LV374 DB
NORTH AMERICA
74LV374 N
74LV374 D
74LV374 DB
UNIT
ns
MHz
pF
pF
PKG. DWG. #
SOT146-1
SOT163-1
SOT339-1
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
1
OE
2, 5, 6, 9, 12,
15, 16, 19
Q0 to Q7
3, 4, 7, 8, 13,
14, 17, 18
D0 to D7
10
GND
11
CP
20
VCC
FUNCTION
Output enable input (active-LOW)
3-State flip-flop outputs
Data inputs
Ground (0V)
Clock input (LOW-to-HIGH, edge-
triggered)
Positive supply voltage
FUNCTION TABLE
OPERATING
MODES
INPUTS
INTERNAL OUTPUTS
OE CP Dn FLIP-FLOPS Q0 to Q7
Load and read L ↑ l
L
L
register
L↑h
H
H
Load register and H ↑ l
L
Z
disable outputs H ↑ h
H
Z
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L = LOW voltage level
l
= LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
Z = High impedance OFF-state
↑ = LOW–to–HIGH clock transition
1997 Mar 20
2
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