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AD7228KNZ 查看數據表(PDF) - Analog Devices

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AD7228KNZ
ADI
Analog Devices ADI
AD7228KNZ Datasheet PDF : 15 Pages
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Data Sheet
AD7228
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VD0 1
VOUT8 2
VOUT7 3
VOUT6 4
VOUT5 5
VOUT4 6
VOUT3 7
VOUT2 8
VOUT1 9
VSS 10
VREF 11
GND 12
AD7228
TOP VIEW
(Not to Scale)
24 A0
23 A1
22 A2
21 WR
20 DB0 (LSB)
19 DB1
18 DB2
17 DB3
16 DB4
15 DB5
14 DB6
13 DB7 (MSB)
4 3 2 1 28 27 26
VOUT6 5
VOUT5 6
VOUT4 7
DNC 8
VOUT3 9
VOUT2 10
VOUT1 11
AD7228
TOP VIEW
(Not to Scale)
25 WR
24 DB0
23 DB1
22 DNC
21 DB2
20 DB3
19 DB4
12 13 14 15 16 17 18
Figure 3. 24-Lead PDIP, CERDIP, and SOIC Pin Configuration
DNC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
Figure 4. 28-Lead PLCC Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
24-Lead PDIP,
CERDIP, and SOIC
28-Lead
PLCC
Mnemonic
1
2
VDD
2
3
VOUT8
3
4
VOUT7
4
5
VOUT6
5
6
VOUT5
6
7
VOUT4
1, 8, 15, 22 DNC
7
9
VOUT3
8
10
VOUT2
9
11
VOUT1
10
12
VSS
11
13
VREF
12
14
GND
13
16
DB7
14
17
DB6
15
18
DB5
16
19
DB4
17
20
DB3
18
21
DB2
19
23
DB1
20
24
DB0
21
25
WR
22
26
A2
23
27
A1
24
28
A0
Description
Positive Supply Voltage This device can be operated from a supply of 10.8 V to 16.5 V.
Analog Output Voltage of DAC 8.
Analog Output Voltage of DAC 7.
Analog Output Voltage of DAC 6.
Analog Output Voltage of DAC 5.
Analog Output Voltage of DAC 4.
Do Not Connect. Do not connect to this pin.
Analog Output Voltage of DAC 3.
Analog Output Voltage of DAC 2.
Analog Output Voltage of DAC 1.
Negative Supply Voltage. This device can be operated from a supply of −5.5 V to −4.5 V.
DAC Reference Voltage Input.
Ground Pin.
Parallel Data Bit 7.
Parallel Data Bit 6.
Parallel Data Bit 5.
Parallel Data Bit 4.
Parallel Data Bit 3.
Parallel Data Bit 2.
Parallel Data Bit 1.
Parallel Data Bit 0.
Write Control Digital Input In, Active Low. WR transfers shift register data to the DAC
register on the rising edge. The signal level on this pin must be ≤ VDD + 0.3 V.
Address Pin 2. The signal level on this pin must be ≤ VDD + 0.3 V.
Address Pin 1. The signal level on this pin must be ≤ VDD + 0.3 V.
Address Pin 0. The signal level on this pin must be ≤ VDD + 0.3 V.
Rev. D | Page 7 of 15

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