AD7228 查看數據表（PDF） - Analog Devices
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AD7228 Datasheet PDF : 15 Pages
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Data Sheet
AD7228
Interface Logic Information
The A0, A1, and A2 address lines select which DAC accepts
data from the input port. Table 6 shows the selection table for
the eight DACs and Figure 8 shows the input control logic.
When the WR signal is low, the input latch of the selected DAC
is transparent, and its output responds to activity on the data
bus. The data is latched into the addressed DAC latch on the
rising edge of WR. While WR is high, the analog outputs
remain at the value corresponding to the data held in their
respective latches.
Table 6. AD7228 Truth Table
Control Inputs
WR
A2
A1
A0
High
X1
X
X
Low
Low to High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
High
High
High
1 X means don’t care.
Low
Low
Low
High
High
Low
Low
High
High
Low
Low
High
Low
High
Low
High
Low
High
Operation
No operation, device
not selected
DAC 1 transparent
DAC 1 latched
DAC 2 transparent
DAC 3 transparent
DAC 4 transparent
DAC 5 transparent
DAC 6 transparent
DAC 7 transparent
DAC 8 transparent
A0
A1
1-OF-8
DECODER
A2
WR
TO DAC 1 LATCH
TO DAC 2 LATCH
TO DAC 3 LATCH
TO DAC 4 LATCH
TO DAC 5 LATCH
TO DAC 6 LATCH
TO DAC 7 LATCH
TO DAC 8 LATCH
Figure 8. Input Control Logic
Supply Current
The AD7228 has a maximum IDD specification of 20 mA and a
maximum ISS of 18 mA over the −40°C to +85°C temperature
range. Figure 9 shows a typical plot of power supply current vs.
temperature.
16
14
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
–60 –40 –20
VVDSSD
=
=
+15V
–5V
IDD
ISS
0 20 40 60 80
TEMPERATURE (°C)
100 120 140
Figure 9. Power Supply Current vs. Temperature
Applying the AD7228 Unipolar Output Operation
Unipolar output operation is the basic mode of operation for
each channel of the AD7228 and the output voltage has the same
positive polarity as VREF. Connections for unipolar output operat-
ion are shown in Figure 10. The AD7228 can be operated from
single or dual supplies. The voltage at the reference input must
never be negative with respect to GND. Failure to observe this
precaution may cause parasitic transistor action and possible
device destruction. The code table for unipolar output operation
is shown in Table 7.
+12V TO +15V
VREF
11
VDD
1
LATCH 1
DAC 1
1
9 VOUT1
LATCH 2
DAC 2
2
8 VOUT2
LATCH 3
DAC 3
3
7 VOUT3
MSB
13
DATA
BUS
20
LSB
LATCH 4
LATCH 5
LATCH 6
DAC 4
DAC 5
DAC 6
4
6 VOUT4
5
5 VOUT5
6
4 VOUT6
LATCH 7
DAC 7
7
3 VOUT7
LATCH 8
DAC 8
8
2 VOUT8
WR 21
A2 22
A1 23
A0 24
Rev. D | Page 9 of 15
CONTROL
LOGIC
AD7228
10
VSS
12
GND
0V OR –5V
Figure 10. Unipolar Output Circuit
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