MB90099 查看數據表（PDF） - Fujitsu
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MB90099 Datasheet PDF : 36 Pages
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MB90099
s PIN DESCRIPTIONS
Pin no.
Pin name I/O
SSOP FLGA
1
A3 SCLK
I
2
A2
CS
I
3
B1
SIN
I
4
C1 RESET
I
5
D1
VDD
6
E1
SDR
I
7
F1
N.C.
8
G1
EXD
I
9
H2 TEST
I
10 H3
GND
11 H4 BLKC
O
12 H5 TESTO O
13 G6 BLKB
O
15 E6 BLKA
O
14 F6
VC3
O
16 D6
VC2
O
17 C6
VC1
O
18 B6
VC0
O
19 A5 VSYNC
I
20 A4 HSYNC
I
Circuit
type
Function
A
Shift clock input pin for serial transfer. This pin has an internal pull-
up resistor.
A
Chip select pin. Input a low level signal during serial transfer. This
pin has an internal pull-up resistor.
A Serial data input pin. This pin has an internal pull-up resistor.
B Reset input pin. Input a low level signal at power-on time.
+3 V power supply pin.
Data input direction select pin for serial transfer. Input a low level
C signal at LSB-first transfer mode, or a high level signal at MSB-first
transfer mode.
Not connected. This pin should be left open.
B Display dot clock input pin.
C LSI test input pin. Input a low level signal during normal use.
Ground pin.
D Display period signal output pin for output channel C.
D LSI test output pin. This pin should be left open during normal use.
D Display period signal output pin for output channel B.
D Display period signal output pin for output channel A.
D Color code signal output pins.
B Vertical synchronization signal input pin.
B Horizontal synchronization signal input pin.
5
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