LC6543N/F/L 查看數據表（PDF） - SANYO -> Panasonic
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LC6543N/F/L Datasheet PDF : 14 Pages
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LC65P29
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Output voltage
Input voltage
I/O voltage
Peak output current
Average output current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
Applicable
pins/notes
Conditions
Ratings
Unit
min
typ
max
VDD max VDD
VO
OSC2
–0.3
+7.0 V
Values up to the generated voltage
are allowed.
V
VI1 OSC1*1
VI2 TEST, RES
Ports with
VI3
PE specifications
–0.3
–0.3
–0.3
VDD + 0.3
V
VDD + 0.3
V
VDD + 0.3
V
VIO
IOP
IOA
Σ IOA1
Σ IOA2
PA, PC, PD
PA, PC, PD
PA, PC, PD
PA
PC, PD
The 100 ms average per pin
The total current for pins PA0 to PA3*2
The total current for pins PC0 to PC3 and
PD0 to PD3*3
–0.3
–2
–2
–6
–14
+15 mA
+20 mA
+20 mA
+40 mA
+90 mA
Pdmax1
Ta = –30 to +70°C(DIP24S)
360 mW
Pdmax2
Ta = –30 to +70°C(MFP30S)
150 mW
Topr
–30
+70 °C
Tstg
–55
+125 °C
Notes: 1. Values up to the generated oscillator amplitude are allowed when driven internally using the guaranteed circuit constant values with the oscillator
circuit shown in figure 2.
2. The average over a 100 ms period.
Allowable Operating Conditions at Ta = –30 to +70°C, VSS = 0 V, VDD = 3.0 to 6.0 V
Parameter
Operating supply voltage
Standby supply voltage
High-level input voltage
Low-level input voltage
Operating frequency (cycle time)
Frequency
Symbol
VDD
VST
VIH1
Applicable
pins/notes
VDD
VDD
PA, PC, PD
VIH2 PE
VIH3 RES
VIH4 OSC1
VIL1 PA, PC, PD
VIL2 PE
VIL3 OSC1
VIL4
VIL5
fop(tCYC)
TEST
RES
fext(text) OSC1
Conditions
VDD [V]
RAM and register retention *
Output n-channel transistor off
When the port E input option
is selected
1.8 to6.0
When the RC oscillator and
external clock option is selected
Output n-channel transistor off
When the port E input option
is selected
When the RC oscillator and
external clock option is selected
See Figure 1
min
3.0
1.8
0.7 VDD
0.7 VDD
0.8 VDD
0.8 VDD
VSS
VSS
VSS
VSS
VSS
200 (20)
200 (20)
Ratings
typ
Unit
max
6.0 V
6.0 V
13.5 V
VDD
V
VDD
V
VDD
V
0.3 VDD
V
0.3 VDD
V
0.25 VDD
V
0.3 VDD
0.25 VDD
4330 (0.92)
V
V
kHz (µs)
4330 (0.92) kHz (µs)
Pulse width
textH, textL OSC1
See Figure 1
69
ns
Rise and fall times
textR, textF OSC1
See Figure 1
50 ns
Cext OSC1, OSC2 See Figure 2
4 to 6
220 ±5%
pF
Two-pin RC oscillator
Ceramic oscillator
Cext
Rext
Rext
OSC1, OSC2
OSC1, OSC2
OSC1, OSC2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
220 ±5%
pF
4 to 6
6.8 ±1%
kΩ
15.0 ±1%
kΩ
See Table 1
Note *: Applications must maintain the operating supply voltage (VDD) until the IC has entered the standby state when a HALT instruction is executed.
Also, applications must assure that chattering (key bounce) noise is not input to the PA3 pin during a HALT instruction execution cycle.
No. 5894-10/14
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