ORT4622BC432I 查看數據表（PDF） - Agere -> LSI Corporation

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ORT4622BC432I

ORCA® ORT4622 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver

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ORCA ORT4622 FPSC

Four-Channel x 622 Mbits/s Backplane Transceiver

Preliminary Data Sheet

March 2000

ORT4622 Overview (continued)

HSI Interface

The high-speed interconnect (HSI) macrocell is used

for clock/data recovery and MUX/deMUX between

77.76 MHz byte-wide internal data buses and

622 Mbits/s external serial links.

The HSI interface receives four 622 Mbits/s serial input

data streams from the LVDS inputs and provides four

independent 77.76 MHz byte-wide data streams and

recovered clock to the STM macro. There is no require-

ment for bit alignment since SONET type framing will

take place inside the ORT4622 core. For transmit, the

HSI converts four byte-wide 77.76 MHz data streams to

serial streams at 622 Mbits/s at the LVDS outputs.

STM Macrocell

The STM portion of the embedded core consists of

transmitter (Tx) and receiver (Rx) sections. The

receiver receives four byte-wide data streams at

77.76 MHz and the associated clocks from the HSI. In

the Rx section, the incoming streams are SONET

framed and descrambled before they are written into a

FIFO which absorbs phase and delay variations and

allows the shift to the system clock. The TOH is then

extracted and sent out on the four serial ports. The

pointer Mover consists of three blocks: pointer inter-

preter, elastic store, and pointer generator. The pointer

interpreter finds the synchronous transport signal

(STS) synchronous payload envelopes (SPE) and

places it into a small elastic store from which the

pointer generator will produce four byte-wide STS-12

streams of data that are aligned to the system timing

pulse.

In the Tx section, transmitted data for each channel is

received through a parallel bus and a serial port from

the FPGA circuit. TOH bytes are received from the

serial input port and can be optionally inserted from

programmable registers or serial inputs to the STS-12

frame via the TOH processor. Each of the four parallel

input buses is synchronized to a free-running system

clock. Then the SPE and TOH data is transferred to the

HSI.

The STM macrocell also has a scrambler/descrambler

disable feature, allowing the user to disable the scram-

bler of the transmitter and the descrambler of the

receiver. Also, unused channels can be disabled to

reduce power dissipation.

CPU Interface

The embedded core has a dedicated, asynchronous,

MPC860 compatible, CPU interface that is used for de-

vice setup, control, and monitoring. Dual sets of I/O pins

of this CPU interface with a bit stream configurable

scheme provide designers a convenient and flexible op-

tion for configuration. One set of CPU I/O pins goes off

chip allowing direct connection with an onboard CPU.

Another set of CPU I/O pins is available to the FPGA

logic allowing for a stand-alone system free of an exter-

nal CPU interface, or for itegration into the Series 3

FPGA MPI interface.

The CPU interface is composed of an 8-bit data bus, a

7-bit address bus, a chip select signal, a read/write sig-

nal, and an interrupt signal.

FPGA Interface

The FPGA logic will receive/transmit frame-aligned

streams of 77.76 MHz data (maximum of four streams

in each direction) from/to the backplane transceiver

embedded core. All frames transmitted to the FPGA

will be aligned to the FPGA frame pulse which will be

provided by the FPGA user’s logic to the STM macro.

All frames received from the FPGA logic will be aligned

to the system frame pulse that will be supplied to the

STM macro from the FPGA user’s logic.

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