ORT4622BC432I 查看數據表（PDF） - Agere -> LSI Corporation

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ORT4622BC432I

ORCA® ORT4622 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver

Agere -> LSI Corporation 

Preliminary Data Sheet

March 2000

ORCA ORT4622 FPSC

Four-Channel x 622 Mbits/s Backplane Transceiver

Table of Contents (continued)

Figure

Page

Figure 12. Serial Configuration Data Format—

Explicit Mode............................................................ 37

Figure 13. Sample Power Supply Filter Network for

Analog HSI Power Supply Pins................................ 42

Figure 14. Transmit Parallel Port Timing

(Backplane -> FPGA)............................................... 48

Figure 15. Transmit Transport Delay

(FPGA -> Backplane)............................................... 49

Figure 16. Receive Parallel Port Timing

(Backplane -> FPGA)............................................... 50

Figure 17. Protection Switch Timing ........................... 51

Figure 18. TOH Input Serial Port Timing

(FPGA -> Backplane)............................................... 52

Figure 19. TOH Output Serial Port Timing

(Backplane -> FPGA)............................................... 53

Figure 20. CPU Write Transaction .............................. 54

Figure 21. CPU Read Transaction.............................. 55

Figure 22. ac Test Loads ............................................ 56

Figure 23. Output Buffer Delays ................................. 56

Figure 24. Input Buffer Delays .................................... 56

Figure 25. Sinklim (TJ = 25 °C, VDD = 3.3 V).............. 57

Figure 26. Slewlim (TJ = 25 °C, VDD = 3.3 V) ............. 57

Figure 27. Fast (TJ = 25 °C, VDD = 3.3 V) .................. 57

Figure 28. Sinklim (TJ = 125 °C, VDD = 3.0 V)............ 57

Figure 29. Slewlim (TJ = 125 °C, VDD = 3.0 V) ........... 57

Figure 30. Fast (TJ = 125 °C, VDD = 3.0 V) ................ 57

Figure 31. LVDS Driver and Receiver and

Associated Internal Components ............................. 58

Figure 32. LVDS Driver and Receiver......................... 58

Figure 33. LVDS Driver............................................... 58

Figure 34. Package Parasitics .................................... 85

List of Tables

Table 1. ORCA ORT4622—Available

FPGA Logic.............................................................. 1

Table 2. ORT4622 Array ............................................ 9

Table 3. Transmitter TOH on LVDS Output

(Transparent Mode).................................................. 17

Table 4. Transmitter TOH on LVDS Output

(TOH Insert Mode) ................................................... 17

Table 5. Valid Starting Positions for an STS-Mc ........ 21

Table 6. Receiver TOH (Output Parallel Bus)............. 23

Table 7. SPE and C1J1 Functionality ........................ 24

Table 8. Structural Register Elements ...................... 26

Table 9. Memory Map ............................................... 27

Table 10. Memory Map Bit Descriptions .................... 31

Table 11. Configuration Frame Format and

Contents................................................................... 37

Table 12. Configuration Modes .................................. 38

Table 13. Absolute Maximum Ratings........................ 39

Table 14. Recommend Operating Conditions ............ 39

Table

Page

Table 15. General Electrical Characteristics ..............39

Table 16. Electrical Characteristics for FPGA I/O.......40

Table 17. Electrical Characteristics for Embedded

Core I/O Other than LVDS I/O ..................................40

Table 18. Jitter Tolerance ...........................................41

Table 19. PLL .............................................................41

Table 20. Input Reference Clock ................................41

Table 21. LVDS Driver dc Data ..................................43

Table 22. LVDS Driver ac Data ..................................43

Table 23. LVDS Receiver dc Data .............................44

Table 24. LVDS Receiver ac Data .............................44

Table 25. LVDS Receiver Power Consumption ..........44

Table 26. LVDS Operating Parameters.......................44

Table 27. Derating for Commercial Devices

(I/O Supply VDD).......................................................45

Table 28. Derating for Commercial Devices

(I/O Supply VDD2).....................................................45

Table 29. ORT4622 Embedded Core and FPGA

Interface Clock Operation Frequencies ....................46

Table 30. Timing Requirements (Transmit

Parallel Port Timing) ................................................48

Table 31. Timing Requirements

(Transmit Transport Delay) .......................................49

Table 32. Timing Requirements

(Receive Parallel Port Timing) .................................50

Table 33. Timing Requirements

(Protection Switch Timing) ......................................51

Table 34. Timing Requirements

(TOH Input Serial Port Timing) ................................52

Table 35. Timing Requirements

(TOH Output Serial Port Timing) .............................53

Table 36. Timing Requirements

(CPU Write Transaction) ..........................................54

Table 37. Timing Requirements

(CPU Read Transaction) ..........................................55

Table 38. Embedded Block Power Dissipation ...........59

Table 39. FPGA Common-Function

Pin Description .........................................................60

Table 40. FPSC Function Pin Description ...............63

Table 41. Embedded Core/FPGA Interface

Signal Description ...................................................65

Table 42. Embedded Core/FPGA Interface

Signal Locations ....................................................67

Table 43. 432-Pin EBGA Pinout .................................68

Table 44. 680-Pin PBGAM Pinout .............................74

Table 45. ORCA ORT4622 Plastic Package

Thermal Guidelines ..................................................83

Table 46. ORCA ORT4622 Package Parasitics..........84

Table 47. Voltage Options ..........................................89

Table 48. Temperature Options ..................................89

Table 49. Package Type Options ................................90

Table 50. ORCA Series 3+ Package Matrix ...............90

Lucent Technologies Inc.

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