ORT4622BC432I 查看數據表（PDF） - Agere -> LSI Corporation

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ORT4622BC432I

ORCA® ORT4622 Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver

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Preliminary Data Sheet

March 2000

ORCA ORT4622 FPSC

Four-Channel x 622 Mbits/s Backplane Transceiver

Description

What Is an FPSC?

FPSCs, or field-programmable system chips, are

devices that combine field-programmable logic with

ASIC or mask-programmed logic on a single device.

FPSCs provide the time to market and flexibility of

FPGAs, the design effort savings of using soft intellec-

tual property (IP) cores, and the speed, design density,

and economy of ASICs.

FPSC Overview

Lucent’s Series 3+ FPSCs are created from Series 3

ORCA FPGAs. To create a Series 3+ FPSC, several

rows of programmable logic cells (see FPGA Logic

Overview section for FPGA logic details) are removed

from a Series 3 ORCA FPGA, and the area is replaced

with an embedded logic core. Other than replacing

some FPGA gates with ASIC gates, at greater than

10:1 efficiency, none of the FPGA functionality is

changed—all of the Series 3 FPGA capability is

retained: MPI, PCMs, boundary scan, etc. The rows of

programmable logic are replaced at the bottom of the

device, allowing pins on the bottom and sides of the

replaced rows to be used as I/O pins for the embedded

core. The remainder of the device pins retain their

FPGA functionality as do special function FPGA pins

within the embedded core area.

The embedded cores can take many forms and gener-

ally come from Lucent Technologies ASIC libraries.

Other offerings allow customers to supply their own

core functions for the creation of custom FPSCs.

FPSC Gate Counting

The total gate count for an FPSC is the sum of its

embedded core (standard-cell/ASIC gates) and its

FPGA gates. Because FPGA gates are generally

expressed as a usable range with a nominal value, the

total FPSC gate count is sometimes expressed in the

same manner. Standard-cell ASIC gates are, however,

10 to 25 times more silicon area efficient than FPGA

gates. Therefore, an FPSC with an embedded function

is gate equivalent to an FPGA with a much larger gate

count.

FPGA/Embedded Core Interface

The interface between the FPGA logic and the embed-

ded core is designed to look like FPGA I/Os from the

FPGA side, simplifying interface signal routing and pro-

viding a unified approach with general FPGA design.

Effectively, the FPGA is designed as if signals were

going off of the device to the embedded core, but the

on-chip interface is much faster than going off-chip and

requires less power. All of the delays for the interface

are precharacterized and accounted for in the ORCA

Foundry Development System.

Clock spines also can pass across the FPGA/embed-

ded core boundary. This allows for fast, low-skew

clocking between the FPGA and the embedded core.

Many of the special signals from the FPGA, such as

DONE and global set/reset, are also available to the

embedded core, making it possible to fully integrate the

embedded core with the FPGA as a system.

For even greater system flexibility, FPGA configuration

RAMs are available for use by the embedded core.

This allows for user-programmable options in the

embedded core, in turn allowing for greater flexibility.

Multiple embedded core configurations may be

designed into a single device with user-programmable

control over which configurations are implemented, as

well as the capability to change core functionality sim-

ply by reconfiguring the device.

ORCA Foundry Development System

The ORCA Foundry Development System is used to

process a design from a netlist to a configured FPSC.

This system is used to map a design onto the ORCA

architecture and then place and route it using ORCA

Foundry’s timing-driven tools. The development system

also includes interfaces to, and libraries for, other popu-

lar CAE tools for design entry, synthesis, simulation,

and timing analysis.

The ORCA Foundry Development System interfaces to

front-end design entry tools and provides the tools to

produce a configured FPSC. In the design flow, the

user defines the functionality of the FPGA portion of

the FPSC and embedded core settings at two points in

the design flow: at design entry and at the bit stream

generation stage. Following design entry, the develop-

ment system’s map, place, and route tools translate the

netlist into a routed FPSC. A static timing analysis tool

is provided to determine device speed, and a back-

annotated netlist can be created to allow simulation.

Lucent Technologies Inc.

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Lucent Technologies Inc.

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