ORLI10G 查看數據表（PDF） - Agere -> LSI Corporation

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ORLI10G

Quad 2.5 Gbits/s 10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

Agere -> LSI Corporation 

ORCA ORLI10G Quad 2.5 Gbits/s

10 Gbits/s, and 12.5 Gbits/s Line Interface FPSC

Data Sheet

October 2001

Programmable Logic System Features

s PCI local bus compliant for FPGA I/Os.

s Improved PowerPC®/PowerQUICC 860 and

PowerPC/PowerQUICC II MPC8260 high-speed

synchronous microprocessor interface can be used

for configuration, readback, device control, and

device status, as well as for a general-purpose

interface to the FPGA logic, RAMs, and embedded

standard-cell blocks. Glueless interface to

synchronous PowerPC processors with user-

configurable address space provided.

s New embedded AMBA™ specification 2.0 AHB

system bus (ARM ® processor) facilitates

communication among the microprocessor interface,

configuration logic, embedded block RAM, FPGA

logic, and embedded standard cell blocks.

s Variable-size bused readback of configuration data

capability with the built-in microprocessor interface

and system bus.

s Internal, 3-state, and bidirectional buses with simple

control provided by the SLIC.

s New clock routing structures for global and local

clocking significantly increases speed and reduces

skew (<200 ps for OR4E4).

s New local clock routing structures allow creation of

localized clock trees.

s Two new edge clock structures allow up to six high-

speed clocks on each edge of the device for

improved setup/hold and clock to out performance.

s New double-data rate (DDR) and zero-bus turn-

around (ZBT) memory interfaces support the latest

high-speed memory interfaces.

s New 2x/4x uplink and downlink I/O capabilities

interface high-speed external I/Os to reduced-speed

internal logic.

s ORCA Foundry development system software.

Supported by industry-standard CAE tools for design

entry, synthesis, simulation, and timing analysis.

s Meets universal test and operations PHY interface

for ATM (UTOPIA) Levels 1, 2, and 3 as well as

POS-PHY3. Also meets proposed specifications for

UTOPIA Level 4 and POS-PHY4 for 10 Gbits/s

interfaces.

s Meets POS-PHY3 (2.5 Gbits/s) and POS-PHY4

(10 Gbits/s) interface standards for packet-over-

SONET as defined by the Saturn Group.

6

Agere Systems Inc.

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