HT27C010 查看數據表（PDF） - Holtek Semiconductor

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HT27C010

OTP CMOS 128Kx8-bit EPROM

Holtek Semiconductor 

HT27C010

to output (tCE). Data is available at the outputs

(tOE) after the falling edge of OE, assuming the

CE has been LOW and addresses have been

stable for at least tACC-tOE.

Standby mode

The HT27C010 has CMOS standby mode which

reduces the maximum VCC current to 10µA. It

is placed in CMOS standby when CE is at

VCC±0.3V. The HT27C010 also has a TTL-

standby mode which reduces the maximum

VCC current to 1.0mA. It is placed in TTL-

standby when CE is at VIH. When in standby

mode, the outputs are in a high-impedance

state, independent of the OE input.

Two-line output control function

To accommodate multiple memory connections,

a two-line control function is provided to allow

for:

• Low memory power dissipation

• Assurance that output bus contention will not

occur

It is recommended that CE be decoded and used

as the primary device-selection function, while

OE be made a common connection to the READ

line from the system control bus. This assures

that all deselected memory devices are in their

low-power standby mode and that the output

pins are only active when data is desired from a

particular memory device.

System considerations

During the switch between active and standby

conditions, transient current peaks are pro-

duced on the rising and falling edges of Chip

Enable. The magnitude of these transient cur-

rent peaks is dependent on the output capaci-

tance loading of the device. At a minimum, a

0.1µF ceramic capacitor (high frequency, low

inherent inductance) should be used on each

device between VCC and VPP to minimize tran-

sient effects. In addition, to overcome the volt-

age drop caused by the inductive effects of the

printed circuit board traces on EPROM arrays,

a 4.7µF bulk electrolytic capacitor should be

used between VCC and VPP for each eight de-

vices. The location of the capacitor should be

close to where the power supply is connected to

the array.

Operation mode truth table

All the operation modes are shown in the table following.

Mode

CE

OE PGM A0

A1

A9 VPP Output

Read

VIL

VIL X (2)

X

Output Disable

VIL

VIH

X

X

Standby (TTL)

VIH

X

X

X

Standby (CMOS)

VCC± 0.3V X

X

X

Program

VIL

VIH

VIL

X

Program Verify

VIL

VIL

VIH

X

Product Inhibit

VIH

X

X

X

Manufacturer Code (3)

VIL

VIL

X

VIL

Device Type Code (3)

VIL

VIL

X

VIH

X

X

VCC Dout

X

X

VCC High Z

X

X

VCC High Z

X

X

VCC High Z

X

X

VPP

DIN

X

X

VPP

DOUT

X

X

VPP High Z

VIH VH (1) VCC

1C

VIH VH (1) VCC

01

Notes: (1) VH=12.0V ± 0.5V

(2) X=Either VIH or VIL

(3) For Manufacturer Code and Device Code, A1=VIH, When A1=VIL, both

codes will read 7F

7

6th May ’99

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