W90210F 查看數據表（PDF） - Winbond

零件编号

产品描述 (功能)

生产厂家

W90210F

PA-RISC Embedded Controller

Winbond 

W90210F

2. Features

Main features of the W90210F

• PA-RISC architecture

PA-RISC 1.1 third edition instruction set

PA-RISC level zero implementation

Support PA-RISC Multimedia Extension 1.0 instruction set

W90K binary compatible for user software

• High-performance implementation

Five-stage pipeline

Precise, efficient handling of pipeline stalls and exceptions

Delayed branch with static branch prediction

Forward: not taken

Backward: taken

One-cycle stall when prediction is wrong

HIT under miss

Both load and store can be queued when miss

Load/store single cycle execution after previous miss

• On-chip cache memory

Internal I-cache: Direct mapped, 4 KB cache (256 entries, four words/entry)

Wrap around fetching when cache miss

Cache freeze capability

Internal D-cache: 2-way set associative, 2 KB cache ×(264 entries, four words/entry)

Write-back cache with write buffer

Write-through option

New line send to CPU before dirty line write back

• Enhanced debug capability

Debug SFU supports both instruction breakpoints and data breakpoints

• High on-chip integration and simple I/O interface

486-like bus interface for CPU core

Memory controller to support four banks of DRAM and ROM/FLASH ROM

2-channel 8-bit DMA controller

PCI bridge

Two Serial ports with FIFO

Extended Capabilities Port (ECP)

Two 24-bit timer/counters

• Power Down mode

Provide power down mode for power saving operation

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The above information is the exclusive intellectual property of Winbond Electronics Corp. and shall not be disclosed, distributed or reproduced without permission from Winbond.

Version 1.4, 10/8/97

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