82375SB 查看數據表（PDF） - Intel

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产品描述 (功能)

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82375SB

PCI-EISA BRIDGE (PCEB)

Intel 

82375EB SB

For EISA-initiated transfers to the PCI Bus the PCEB is a PCI master The PCEB permits EISA devices to

access either PCI memory or I O While all PCI I O transfers are single cycle PCI memory cycles can be

either single cycle or burst depending on the status of the PCEB’s Line Buffers During EISA reads of PCI

memory the PCEB uses a burst read cycle of four Dwords to prefetch data into a Line Buffer During EISA-to-

PCI memory writes the PCEB uses PCI burst cycles to flush the Line Buffers The PCEB contains a program-

mable Master Latency Timer that provides the PCEB with a guaranteed time slice on the PCI Bus after which it

surrenders the bus

As a master on the PCI Bus the PCEB generates address and command signals (C BE 3 0 ) address parity

for read and write cycles and data parity for write cycles As a slave the PCEB generates data parity for read

cycles Parity checking is not supported

The PCEB as a resource can be locked by any PCI master In the context of locked cycles the entire PCEB

subsystem (including the EISA Bus) is considered a single resource

PCI Bus Arbitration

The PCI arbiter supports six PCI masters the Host PCI bridge PCEB and four other PCI masters The arbiter

can be programmed for twelve fixed priority schemes a rotating scheme or a combination of the fixed and

rotating schemes The arbiter can be programmed for bus parking that permits the Host PCI Bridge default

access to the PCI Bus when no other device is requesting service The arbiter also contains an efficient PCI

retry mechanism to minimize PCI Bus thrashing when the PCEB generates a retry

EISA Bus Interface

The PCEB contains a fully EISA-compatible master and slave interface The PCEB directly drives eight EISA

slots without external data or address buffering The PCEB is only a master or slave on the EISA Bus for

transfers between the EISA Bus and PCI Bus For transfers contained to the EISA Bus the PCEB is never a

master or slave However the data swap buffers contained in the PCEB are involved in these transfers if data

size translation is needed The PCEB also provides support for I O recovery

EISA ISA masters and DMA can access PCI memory or I O The PCEB only forwards EISA cycles to the PCI

Bus if the address of the transfer matches one of the address ranges programmed into the PCEB for EISA-to-

PCI positive decode This includes the main memory segments used for generating MEMCS from the EISA

Bus one of the four programmable memory regions or one of the four programmable I O regions For EISA-

initiated accesses to the PCI Bus the PCEB is a slave on the EISA Bus I O accesses are always non-buffered

and memory accesses can be either non-buffered or buffered via the Line Buffers For buffered accesses

burst cycles are supported

During PCI-initiated cycles to the EISA Bus the PCEB is an EISA master Single cycle transfers are used for I

O and memory read write cycles from PCI to EISA

PCI EISA Address Decoding

The PCEB contains two address decoders one to decode PCI-initiated cycles and the other to decode EISA-

initiated cycles The two decoders permit the PCI and EISA Buses to operate concurrently

The PCEB can also be programmed to provide main memory address decoding on behalf of the Host PCI

bridge When programmed the PCEB monitors the PCI and EISA bus cycle addresses and generates a

memory chip select signal (MEMCS ) indicating that the current cycle is targeted to main memory residing

behind the Host PCI bridge Programmable features include read write attributes for specific memory seg-

ments and the enabling disabling of a memory hole If not used the MEMCS feature can be disabled

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