82375SB 查看數據表（PDF） - Intel

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82375SB

PCI-EISA BRIDGE (PCEB)

Intel 

82375EB SB

1 0 ARCHITECTURAL OVERVIEW

The PCI-EISA bridge chip set provides an I O subsystem core for the next generation of high-performance

personal computers (e g those based on the Intel486TM or Pentium processors) System designers can take

advantage of the power of the PCI local bus while maintaining access to the large base of EISA and ISA

expansion cards and corresponding software applications Extensive buffering and buffer management within

the PCI-EISA bridge ensures maximum efficiency in both bus environments

The chip set consists of two components the 82375EB PCI-EISA Bridge (PCEB) and the 82374EB EISA

System Component (ESC) These components work in tandem to provide an EISA I O subsystem interface for

personal computer platforms based on the PCI standard This section provides an overview of the PCI and

EISA Bus hierarchy followed by an overview of the PCEB and ESC components

Bus Hierarchy Concurrent Operations

Figure 1 shows a block diagram of a typical system using the PCI-EISA Bridge chip set The system contains

three levels of buses structured in the following hierarchy

 Host Bus as the execution bus

 PCI Bus as a primary I O bus

 EISA Bus as a secondary I O bus

PCI Bus

The PCI Bus has been defined to address the growing industry needs for a standardized local bus that is not

directly dependent on the speed and the size of the processor bus New generations of personal computer

system software such as WindowsTM and Win-NTTM with sophisticated graphical interfaces multi-tasking and

multi-threading bring new requirements that traditional PC I O architectures can not satisfy In addition to the

higher bandwidth reliability and robustness of the I O subsystem are becoming increasingly important The

PCI environment addresses these needs and provides an upgrade path for the future PCI features include

 Processor independent

 Multiplexed burst mode operation

 Synchronous up to 33 MHz

 120 MByte sec usable throughput (132 MByte sec peak) for 32-bit data path

 240 MByte sec usable throughput (264 MByte sec peak) for 64-bit data path

 Optional 64-bit data path with operations that are transparent with the 32-bit data path

 Low latency random access (60 ns write access latency to slaves from a master parked on the bus)

 Capable of full concurrency with processor memory subsystem

 Full multi-master capability allowing any PCI master peer-to-peer access to any PCI slave

 Hidden (overlapped) central arbitration

 Low pin count for cost effective component packaging (multiplexed address data)

 Address and data parity

 Three physical address spaces memory I O and configuration

 Comprehensive support for autoconfiguration through a defined set of standard configuration functions

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