MT88E39 查看數據表（PDF） - Mitel Networks

零件编号

产品描述 (功能)

生产厂家

MT88E39

Calling Number Identification Circuit

Mitel Networks 

Advance Information

MT88E39

signals. The user may choose to ignore these

outputs when FSK data is not expected, or force the

MT88E39 into its power down mode.

Power Down Mode

For applications requiring reduced power

consumption, the MT88E39 can be forced into power

down when it is not needed. This is done by pulling

the PWDN pin high. In power down mode, the

oscillator, op-amp and internal circuitry are all

disabled and the MT88E39 will not react to the input

signal. DR and CD are at high impedance or at logic

high (modes 0 and 1 respectively). In mode 0, DATA

and DCLK are at logic high. The MT88E39 can be

awakened for reception of the FSK signal by pulling

the PWDN pin low.

Carrier Detect

The carrier detector provides an indication of the

presence of a signal in the FSK frequency band. It

detects the presence of a signal of sufficient

amplitude at the output of the FSK bandpass filter.

The signal is qualified by a digital algorithm before

the CD output is set low to indicate carrier detection.

A 10ms hysteresis is provided to allow for

momentary signal drop out once CD has been

activated. CD is released when there is no activity at

the FSK bandpass filter output for 10 ms.

When CD is inactive (high), the raw output of the

demodulator is ignored by the data timing recovery

circuit (see Figure 1). In mode 0, the DATA pin is

forced high. No DCLK or DR signal is generated. In

mode 1, the internal shift register is not updated and

no DR is generated. If DCLK is clocked (in mode 1),

DATA is undefined.

Note that signals such as CAS, speech and DTMF

tones also lie in the FSK frequency band and the

carrier detector may be activated by these signals.

They will be demodulated and presented as data. To

avoid false data, the PWDN pin should be used to

disable the FSK demodulator when no FSK signal is

expected.

Ringing, on the other hand, does not pose a problem

as it is ignored by the carrier detector.

Crystal Oscillator

The MT88E39 uses either a 3.579545MHz ceramic

resonator or crystal oscillator as the master timing

source.

The crystal specification is as follows:

Frequency:

3.579545 MHz

Frequency tolerance:

±0.2%(-40°C+85°C)

Resonance mode:

Parallel

Load capacitance:

18 pF

Maximum series resistance: 150 ohms

Maximum drive level (mW): 2 mW

e.g. CTS MP036S

MT88E39

OSC1 OSC2

MT88E39

OSC1 OSC2

MT88E39

OSC1 OSC2

to the

3.579545 MHz

next MT88E39

(For 5V application only)

Figure 5 - Common Crystal Connection

For 5V applications any number of MT88E39 devices

can be connected as shown in Figure 5 such that

only one crystal is required. The connection between

OSC2 and OSC1 can be DC coupled as shown, or

the OSC1 input on all devices can be driven from a

CMOS buffer (dc coupled) with the OSC2 outputs left

unconnected.

VRef and CAP Inputs

VRef is the output of a low impedance voltage source

equal to VDD/2 and is used to bias the input op-amp.

A 0.1µF capacitor is required between CAP and VSS

to suppress noise on VRef.

Applications

Table 1 shows the Bellcore and ETSI FSK signal

characteristics. The application circuit in Figure 6 will

meet these requirements.

For 5V designs the input op-amp should be set to

unity gain to meet the Bellcore requirements and

-2.5 dB gain for ETSI requirements.

As supply voltage (VDD) is decreased, the FSK

detect threshold will be lowered. Therefore for

designs operating at other than 5V nominal voltage,

to meet the FSK reject level requirement the gain of

the op-amp should be reduced accordingly.

For 3V designs the gain settings for Bellcore and

ETSI should be -3dB and -5.5dB respectively.

5-5

Share Link: