WM8181 查看數據表（PDF） - Wolfson Microelectronics plc
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WM8181 Datasheet PDF : 14 Pages
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WM8181
Advanced Information
OVERALL TIMING
The WM8181 input sampling, conversion and data output is controlled by externally applied MCLK
and VSMP clocks. Please refer to the Operational Timing Diagrams (Figures 4 and 5) shown at the
end of this section.
12:1 MCLK: VSMP RATIO OPERATION
MCLK can run at speeds of up to 24MHz. VSMP is a pulse one MCLK period long, with 12 times the
period of MCLK. VSMP must cover one rising edge of MCLK.
If VSMP is high for more than one MCLK rising edge, the last MCLK rising edge that is covered is
defined as the starting point and the video signal will be sampled on the next rising edge of MCLK.
Output data being processed at this time may be corrupted.
VSMP should be held low for 11 MCLK rising edges, then pulsed high for the 12th MCLK rising edge
to produce an MCLK:VSMP ratio of 12:1. If VSMP is held low for less than 11 MCLK rising edges,
the device will reset to the starting point and the video signal will be sampled on the next rising edge
of MCLK. Output data being processed during this time may be corrupted.
16:1 MCLK: VSMP RATIO OPERATION
The WM8181 can also operate with an MCLK:VSMP ratio of 16:1. Video signal sampling is
performed in the same manner as in 12:1 operation except that the device will wait an extra four
MCLK periods for the next VSMP pulse to go low before sampling the video signal.
DEVICE LATENCY
For 12:1 operation, the WM8181 will start to output valid data MSB first on the falling edge of MCLK
24.5 MCLK periods after the sampling instant (first rising edge of MCLK after VSMP goes low) for
that pixel. The device continues to output the data on the next 11 falling edges of MCLK
For 16:1 operation, the output latency increases to 32.5 MCLK periods after the sampling instant.
Data is output MSB first on this falling edge of MCLK, and continues over the next 11 falling edges of
MCLK. The four bits between the end of one output and the start of the next will be 0.
POWER DOWN
If VSMP is held high for 64 MCLK rising edges, the device will power down, causing DOUT, VRT,
and VRB to change into a high impedance state. The device will start powering up immediately on
VSMP going low, however VRT and VRB will take some time to recover and settle, depending on
how their voltages have decayed during power down and the decoupling capacitors used. Typically
for 1µF decoupling capacitors the amount of time taken for VRT and VRB to recover may be up to
10ms. If 0.1µF capacitors are used, this time will decrease to typically 1ms.
OPERATIONAL TIMING DIAGRAMS
CCD Video Pixel 0
Outputs
Reset
Video Pixel 1
Reset
Video Pixel 2
Reset
Video Pixel 3
MCLK
VSMP
S/H
DOUT
LATENCY = 24.5 MCLK PERIODS
D11 → D0 PIXEL - 2
D11 → D0 PIXEL - 1
D11 → D0 PIXEL 0
Figure 4 12:1 Operation
WOLFSON MICROELECTRONICS LTD
AI Rev 3.0 January 2000
8
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