A75 查看數據表（PDF） - Intel

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A75

PENTIUM® PROCESSOR

Intel 

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

Symbol

BF[1:0]

BOFF#

BP[3:2]

PM/BP[1:0]

BRDY#

BRDYC#

BREQ

BUSCHK#

Type*

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Table 2. Quick Pin Reference (Continued)

Name and Function

Bus Frequency determines the bus-to-core frequency ratio. BF[1:0] are sampled

at RESET, and cannot be changed until another non-warm (1 ms) assertion of

RESET. Additionally, BF[1:0] must not change values while RESET is active. See

Table 3 for Bus Frequency Selections.

The backoff input is used to abort all outstanding bus cycles that have not yet

completed. In response to BOFF#, the Pentium processor 75/90/100/120/133/150/

166/200 will float all pins normally floated during bus hold in the next clock. The

processor remains in bus hold until BOFF# is negated, at which time the Pentium

processor 75/90/100/120/133/150/166/200 restarts the aborted bus cycle(s) in

their entirety.

The breakpoint pins (BP3-0) correspond to the debug registers, DR3-DR0.

These pins externally indicate a breakpoint match when the debug registers are

programmed to test for breakpoint matches.

BP1 and BP0 are multiplexed with the performance monitoring pins (PM1 and

PM0). The PB1 and PB0 bits in the Debug Mode Control Register determine if the

pins are configured as breakpoint or performance monitoring pins. The pins come

out of RESET configured for performance monitoring.

The burst ready input indicates that the external system has presented valid data

on the data pins in response to a read or that the external system has accepted

the Pentium processor 75/90/100/120/133/150/166/200 data in response to a write

request. This signal is sampled in the T2, T12 and T2P bus states.

This signal has the same functionality as BRDY#.

The bus request output indicates to the external system that the Pentium

processor 75/90/100/120/133/150/166/200 has internally generated a bus request.

This signal is always driven whether or not the Pentium processor

75/90/100/120/133/150/166/200 is driving its bus.

The bus check input allows the system to signal an unsuccessful completion of a

bus cycle. If this pin is sampled active, the Pentium processor

75/90/100/120/133/150/166/200 will latch the address and control signals in the

machine check registers. If, in addition, the MCE bit in CR4 is set, the Pentium

processor 75/90/100/120/133/150/166/200 will vector to the machine check

exception.

NOTE:

To assure that BUSCHK# will always be recognized, STPCLK# must be

deasserted any time BUSCHK# is asserted by the system, before the system

allows another external bus cycle. If BUSCHK# is asserted by the system for a

snoop cycle while STPCLK# remains asserted, usually (if MCE=1) the processor

will vector to the exception after STPCLK# is deasserted. But if another snoop to

the same line occurs during STPCLK# assertion, the processor can lose the

BUSCHK# request.

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