A75 查看數據表（PDF） - Intel

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A75

PENTIUM® PROCESSOR

Intel 

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

E

Symbol

IGNNE#

INIT

INTR/LINT0

INV

KEN#

LINT0/INTR

LINT1/NMI

Type*

I

I

I

I

I

I

I

Table 2. Quick Pin Reference (Continued)

Name and Function

This is the ignore numeric error input. This pin has no effect when the NE bit in CR0 is

set to 1. When the CR0.NE bit is 0, and the IGNNE# pin is asserted, the Pentium

processor 75/90/100/120/133/150/166/200 will ignore any pending unmasked numeric

exception and continue executing floating-point instructions for the entire duration that

this pin is asserted. When the CR0.NE bit is 0, IGNNE# is not asserted, a pending

unmasked numeric exception exists (SW.ES = 1), and the floating point instruction is

one of FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI, FDISI, or FSETPM,

the Pentium processor 75/90/100/120/133/150/166/200 will execute the instruction in

spite of the pending exception. When the CR0.NE bit is 0, IGNNE# is not asserted, a

pending unmasked numeric exception exists (SW.ES = 1), and the floating-point

instruction is one other than FINIT, FCLEX, FSTENV, FSAVE, FSTSW, FSTCW, FENI,

FDISI, or FSETPM, the Pentium processor 75/90/100/120/133/

150/166/200 will stop execution and wait for an external interrupt.

IGNNE# is internally masked when the Pentium processor 75/90/100/120/133/150/

166/200 is configured as a Dual processor.

The Pentium processor 75/90/100/120/133/150/166/200 initialization input pin

forces the Pentium processor 75/90/100/120/133/150/166/200 to begin execution

in a known state. The processor state after INIT is the same as the state after

RESET except that the internal caches, write buffers, and floating point registers

retain the values they had prior to INIT. INIT may NOT be used in lieu of RESET

after power-up.

If INIT is sampled high when RESET transitions from high to low, the Pentium

processor 75/90/100/120/133/150/166/200 will perform built-in self test prior to the

start of program execution.

An active maskable interrupt input indicates that an external interrupt has been

generated. If the IF bit in the EFLAGS register is set, the Pentium processor

75/90/100/120/133/150/166/200 will generate two locked interrupt acknowledge

bus cycles and vector to an interrupt handler after the current instruction execution

is completed. INTR must remain active until the first interrupt acknowledge cycle

is generated to assure that the interrupt is recognized.

If the local APIC is enabled, this pin becomes LINT0.

The invalidation input determines the final cache line state (S or I) in case of an

inquire cycle hit. It is sampled together with the address for the inquire cycle in the

clock EADS# is sampled active.

The cache enable pin is used to determine whether the current cycle is cacheable

or not and is consequently used to determine cycle length. When the Pentium

processor 75/90/100/120/133/150/166/200 generates a cycle that can be cached

(CACHE# asserted) and KEN# is active, the cycle will be transformed into a burst

line fill cycle.

If the APIC is enabled, this pin is local interrupt 0. If the APIC is disabled, this pin

is INTR.

If the APIC is enabled, this pin is local interrupt 1. If the APIC is disabled, this pin

is NMI.

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