A75 查看數據表（PDF） - Intel

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A75

PENTIUM® PROCESSOR

Intel 

PENTIUM® PROCESSOR 75/90/100/120/133/150/166/200

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instructions in a single clock. Together, the dual

pipes can issue two integer instructions in one

clock, or one floating point instruction (under certain

circumstances, two floating-point instructions) in

one clock.

Branch prediction is implemented in the Pentium

processors. To support this, Pentium processors

implement two prefetch buffers, one to prefetch

code in a linear fashion, and one that prefetches

code according to the BTB so the needed code is

almost always prefetched before it is needed for

execution.

The floating-point unit has been completely

redesigned over the Intel486 CPU. Faster

algorithms provide up to 10X speed-up for common

operations including add, multiply, and load.

Pentium processors include separate code and data

caches integrated on-chip to meet performance

goals. Each cache is 8 Kbytes in size, with a 32-

byte line size and is 2-way set associative. Each

cache has a dedicated Translation Lookaside Buffer

(TLB) to translate linear addresses to physical

addresses. The data cache is configurable to be

write back or write through on a line-by-line basis

and follows the MESI protocol. The data cache tags

are triple ported to support two data transfers and

an inquire cycle in the same clock. The code cache

is an inherently write-protected cache. The code

cache tags are also triple ported to support

snooping and split line accesses. Individual pages

can be configured as cacheable or non-cacheable

by software or hardware. The caches can be

enabled or disabled by software or hardware.

The Pentium processors have increased the data

bus to 64 bits to improve the data transfer rate.

Burst read and burst write back cycles are

supported by the Pentium processors. In addition,

bus cycle pipelining has been added to allow two

bus cycles to be in progress simultaneously. The

Pentium processors' Memory Management Unit

contains optional extensions to the architecture

which allow 2-Mbyte and 4-Mbyte page sizes.

The Pentium processors have added significant

data integrity and error detection capability. Data

parity checking is still supported on a byte-by-byte

basis. Address parity checking, and internal parity

checking features have been added along with a

new exception, the machine check exception.

In addition, the Pentium processors have

implemented functional redundancy checking to

provide maximum error detection of the processor

and the interface to the processor. When functional

redundancy checking is used, a second processor,

the “checker” is used to execute in lock step with

the “master” processor. The checker samples the

master's outputs and compares those values with

the values it computes internally, and asserts an

error signal if a mismatch occurs.

As more and more functions are integrated on chip,

the complexity of board level testing is increased.

To address this, the Pentium processors have

increased test and debug capability. The Pentium

processors implement IEEE Boundary Scan

(Standard 1149.1). In addition, the Pentium

processors have specified 4 breakpoint pins that

correspond to each of the debug registers and

externally indicate a breakpoint match. Execution

tracing provides external indications when an

instruction has completed execution in either of the

two internal pipelines, or when a branch has been

taken.

System Management Mode (SMM) has been

implemented along with some extensions to the

SMM architecture. Enhancements to the virtual

8086 mode have been made to increase

performance by reducing the number of times it is

necessary to trap to a virtual 8086 monitor.

Figure 1 shows a block diagram of the Pentium

processor 75/90/100/120/133/150/166/200.

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